Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-04-27
2003-03-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S257000, C438S259000, C438S264000, C216S068000, C216S067000, C216S079000
Reexamination Certificate
active
06528332
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to a method and system for avoiding the build up of a polymer during a plasma etch of an intermetal dielectric when deprocessing the semiconductor device.
BACKGROUND OF THE INVENTION
FIG. 1
depicts a conventional method
10
for deprocessing a semiconductor device in order to investigate failures in semiconductor devices. Deprocessing removes portions of the semiconductor device to expose structures that are to be studied to determine whether a fault exists and, if so, the type of the fault. The conventional method
10
is described in conjunction with the semiconductor device
30
depicted in
FIGS. 2A and 2B
. Referring to
FIG. 1
, a top portion of the semiconductor device is thus removed to expose the intermetal dielectric layer, via step
12
. The top portion of the semiconductor device may be mechanically removed or removed in another way. The intermetal dielectric layer exposed is a lower level, such as the intermetal dielectric one layer. The intermetal one dielectric layer insulates the first layer of metal (“metal 1”) from the remainder of the semiconductor device.
FIG. 2A
depict the semiconductor device
30
after the intermetal dielectric layer
32
has been exposed in step
12
. The semiconductor device
30
also includes a local interconnect
34
and a word line
36
above a substrate
31
. The local interconnect
34
is included in the first metal layer.
In general, a reactive ion etch and more particularly an anisotropic plasma etch of the intermetal dielectric is performed at an angle perpendicular to the surface of the semiconductor device. However, in practice the plasma etches in an oblique angle, via step
14
. An oblique angle is an angle that is greater than zero and smaller than 90 degrees from normal to the surface of the semiconductor device
30
. Thus, the direction of the plasma etch is depicted by the arrow
38
in FIG.
2
A. An oblique angle is caused by the magnets inside the system below the semiconductor device
30
. The investigation of the exposed components and subsequent deprocessing can then be performed, via step
16
.
FIG. 2B
depicts the semiconductor device
30
′ after the plasma etch is performed in step
14
. The intermetal dielectric
32
has been removed and thus is not present in FIG.
2
B. Most of the word line
36
′ and the local interconnect
34
′ have been exposed. In addition, a material
40
and
42
has built up on the side of the local interconnect
34
′ and the word line
36
′g respectively, that were shadowed from the direction of the plasma etch. The material
40
and
42
typically includes a polymer. The material
40
and
42
is due to the plasma etch of the intermetal dielectric
32
.
Although the method
10
allows the semiconductor device
30
to be deprocessed, one of ordinary skill in the art will readily realize that the method
10
results in the build up of the material
40
and
42
, described above. The material
40
and
42
may cover some or all of the sides of the local interconnect
34
′ and the word line
36
′. In addition, the material may extend between the local interconnect
34
′ and the word line
36
′. Because the material
40
and
42
covers at least a portion of the sides of the local interconnect
34
′ and the word line
36
′g respectively, any faults at the sides of these local interconnect
34
′ and the word line
36
′ will remain hidden. Similarly, a short between the local interconnect
34
′ or the word line
36
′ and another structure may be hidden by the material
40
and
42
, respectively. Thus, the method
10
may miss some defects in the semiconductor device
30
.
Accordingly, what is needed is a system and method for deprocessing semiconductor devices, particularly at lower layers that allows faults to be uncovered. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for deprocessing a semiconductor device. The semiconductor device has a plurality of structures and an intermetal dielectric layer. The method and system comprise anisotropic plasma etching the intermetal dielectric layer at an oblique angle and rotating the semiconductor device during the plasma etch to reduce or eliminate build up of a material on the plurality of structures due to the plasma etch of the intermetal dielectric layer. In another aspect the method and system include a semiconductor device deprocessed using the method in accordance with the present invention. In another aspect, the present invention comprises a system for deprocessing the semiconductor device. The system includes a chamber having a cavity therein for retaining the semiconductor device during a plasma etch of the intermetal dielectric layer. The system also includes a sample holder, coupled with the chamber, for holding the semiconductor device in the chamber and at least one magnet disposed outside of the chamber. In such a system the sample holder is capable of rotating the semiconductor device during the plasma etch to reduce or eliminate build up of a material on the plurality of structures due to the plasma etch of the intermetal dielectric layer without rotating the at least one magnet.
According to the system and method disclosed herein, the present invention allows a semiconductor device to be deprocessed while reducing the build up of a material during deprocessing.
REFERENCES:
patent: 6046085 (2000-04-01), Chan
patent: 6238588 (2001-05-01), Collins et al.
Hulog Jose
Mahanpour Mehrdad
Massoodi Mohammad
Advanced Micro Devices , Inc.
Nelms David
Sawyer Law Group LLP
Tran Mai-Huong
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