Method and system for reducing leakage current in integrated...

Details Method and system for reducing leakage current in integrated... Method and system for reducing leakage current in integrated...

2005-08-09

2005-08-09

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S536000

Reexamination Certificate

active

06927619

ABSTRACT:
An apparatus for reducing leakage currents in an integrated circuit having logic gates containing PMOS devices and NMOS devices. The apparatus comprises a power management unit capable of: i) applying a fixed VDD supply voltage to body connections of said PMOS devices; ii) applying a fixed VSS supply voltage to body connections of said NMOS devices; iii) applying an adjustable PMOS source voltage to sources of said PMOS devices; and iv) applying an adjustable NMOS source voltage to sources of said NMOS devices.

REFERENCES:
patent: 6175251 (2001-01-01), Horiguchi et al.
patent: 6211725 (2001-04-01), Kang
patent: 6225846 (2001-05-01), Wada et al.
patent: 6552596 (2003-04-01), Cowles et al.
patent: 6559708 (2003-05-01), Notani

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