Method and system for reducing hazards in a flip-flop

Details Method and system for reducing hazards in a flip-flop Method and system for reducing hazards in a flip-flop

2002-01-11

2003-11-11

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S212000, C327S218000

Reexamination Certificate

active

06646487

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to the field of electronic circuit design, and in particular to techniques for reducing hazards in a digital logic circuit, for example, a digital logic flip-flop circuit.
BACKGROUND OF THE INVENTION
The Semi-Dynamic Flip-Flop (SDFF) is one of the high performance flip-flops based on the hybrid concept. In part due to its size, low clock-to-output delay, negative set-up time, and simple topology, it is considered to be one of the fastest flip-flops today. However, the SDFF is susceptible to a hazard condition, when both the input and output are at a high logic value.
FIG. 1
shows a schematic circuit diagram of a typical prior art SDFF. The data input is D
312
, the clock signal is CLK
0
314
, and the outputs are Q
316
and Qbar
317
. The two inverters inv
5
318
and inv
6
319
are a “keeper” circuit which maintains the value of output Qbar
317
and hence output Q
316
. A transparency window for the SDFF is given by the propagation delay of the two inverters, inv
1
350
and inv
2
352
, and the NAND gate
354
. The internal node X
320
of the first stage
330
of the SDFF is set to a high logic level (H), when the clock CLK
0
314
is at a low logic level (L), i.e., the first stage
330
is pre-charged. When the input signal D
312
is H, node X
320
transitions from H to L in the transparency window where both CLK
0
314
and S
356
are H (transistors Mn
1
346
, Mn
2
344
, and Mn
3
342
are on). The second stage
332
captures the transition on node X
320
generated by the first stage
330
and produces output Q
316
. In this case node X
320
sets output Q
316
to H via transistor Mp
2
374
. If input D
312
is L, Mn
2
344
is off and node X
320
remains high during the transparency window. With node X
320
at H, output Q
316
is set at L during the transparency window (transistors Mn
4
370
and Mn
5
372
are on).
FIG. 2
is an example timing diagram for the SDFF schematic circuit diagram of
FIG. 1
showing a glitch in the output. The timing diagram shows the clock signal CLK
0
410
representing the CLK
0
314
in
FIG. 1. D
414
, X
416
, and Q
418
show the signals for D
312
, node X
320
, and Q
316
in
FIG. 1
respectively. From
FIG. 2
, after the rising edge
430
of CLK
0
410
and with D
414
set to L, X
416
remains at H and output Q
418
, due to transistors Mn
4
370
and Mn
5
372
, transitions from H to L
434
. After another rising edge
440
of CLK
0
410
and with D
414
at H, X
416
transitions from H to L
442
due to transistors Mn
1
346
, Mn
2
344
, and Mn
3
342
turning on. Next output Q
418
transitions from L to H
444
due to transistor Mp
2
374
. Thus the L to H transition of output Q, e.g.,
444
, is done using in effect an inverting intermediate node X
320
, while the transition of output Q, e.g.,
434
, from H to L is done directly via nMOS transistors and avoids the slower pMOS transistors. The SDFF is used where the time critical output transitions are from L to H, e.g.,
444
, on output Q
316
, and thus the node X transition, e.g., H to L
442
, is important.
However, the asymmetrical transition times of the SDFF lead to a “static-one-hazard” at the output Q when both input D and output Q are H. In
FIG. 2
, before the rising edge
450
of the CLK
0
410
, X
416
is set (or reset) to H by transistor Mp
1
340
. Because the first stage
330
has a non-zero propagation delay from the time of the rising clock edge
450
to the time X
416
transitions from H to L
454
, the second stage
332
uses the previous X (H). Hence during the time window between the rising edge
450
of the clock CLK
0
410
and the falling edge
454
of X
416
, both Mn
4
370
and Mn
5
372
in
FIG. 1
are on and the output Q
316
is pulled to low logic level (e.g., transition
452
). After the propagation delay, i.e., the falling transition
454
of X
416
, the transistor Mp
2
372
turns on (and Mn
4
370
turns off), and the output Q
316
is pulled to H (e.g., transition
456
). Thus a glitch
462
is caused on the output Q
418
(and Qbar
420
) and makes the use of the SDFF hazardous. In addition the glitch consumes power unnecessarily, as output Q
316
should not change, since input D
312
has not changed.
There is also a problem of power consumption in the unconditional keepers of the SDFF (back-to-back inverters, inv
3
360
and inv
4
362
, and back-to-back inverters, inv
5
318
and inv
6
319
, of FIG.
1
). The keeper is used to hold the value of a dynamic node, e.g., node X
320
or output Q
316
, that would otherwise be in high impedance and thus sensitive to leakage current effects and noise, especially in low-power applications where clock gating techniques are typically employed. The problem is that in order to change the value of the dynamic node, the keeper (two keepers, in the case of the SDFF) has to be overpowered, i.e., the output logic level of the keeper needs to be switched, which increases power consumption.
The power consumption and hazard problems associated with the SDFF, are demonstrative of the same or similar problems with hybrid-type flip-flops in general. Another example of a flip-flop having the same or similar type problems is the Hybrid Latch Flip-Flop (HLFF).
Therefore with the problems of hazard and power consumption with the conventional hybrid-type flip-flop, e.g., SDFF, there is a need for an improved flip-flop with fewer problems, such as fewer hazards or no hazards at all.
SUMMARY OF THE INVENTION
The present invention provides techniques, including a system and method, for reducing hazards in a conventional flip-flop, having a pre-charged stage coupled to an evaluation stage, by allowing a change in the pre-charged stage to settle before the evaluation stage processes the change. One embodiment has a substantially similar delay as the SDFF with fewer hazards and a significant reduction in power consumption.
Broadly, the present invention provides a method that reduces hazards in a flip-flop. In one embodiment this method includes a delayed reset of the output Q. The setting of the output Q, i.e., the second or evaluation stage, is disabled from being set to a low logic level by a delayed clock signal. This leaves time for the internal node X, i.e., output of the first or pre-charged stage, to transition from the high to the low logic level after the rising edge of the clock, without affecting the output Q. Consequently, the glitch that appears at Q in case of SDFF, when both the input D and output Q are at a high logic level, is prevented. In addition, a delayed pre-charge of the first stage is provided in order to prevent another hazard on the output Q. This hazard may occur because the second stage remains enabled until the delayed clock is pulled low. Hence, if the internal node X quickly charges before the second stage is disabled, a glitch on or false switching of output Q may occur. Thus, this embodiment provides a reduced-hazard flip-flop.
In another aspect of the present invention a method is provided for reducing hazards in a flip-flop, with the method including a pre-charged stage coupled to an evaluation stage by at least an internal node. First, the pre-charged stage sets the internal node based on a data input. The evaluation stage is prevented from evaluating the internal node for a predetermined time period. After the predetermined time period, the internal node is evaluated by the evaluation stage to determine an output of the flip-flop.
Yet another aspect of the present invention provides a system for reducing hazards in a hybrid flip-flop including: a pre-charge stage for determining a pre-charge stage output depending upon a data input during a transparency window; and an evaluation stage for evaluating the pre-charge stage output to produce a data output during the transparency window, where the evaluation stage is enabled to change the data output to a low logic level only after the pre-charge stage determines the pre-charge stage output. The transparency window includes a time period when the pre-charge stage output is logically equiv

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