Method and system for reducing average branch resolution time an

Details Method and system for reducing average branch resolution time an Method and system for reducing average branch resolution time an

1996-09-30

1998-09-08

Lall, Parshotam S.

395392, G06F 938

Patent

active

058058761

ABSTRACT:
Logic circuitry provides a fast resolution of conditional branch instructions in a high-performance superscalar processor. The logic circuitry facilities early (fast) resolution of a subset of conditional branches located within the first position of the primary instruction buffer within the processor enabling the overall branch processing logic to bypass history table-based prediction logic for such branches without crossing the cycle boundary. Thus, penalties associated with possible mispredictions for this subset of conditional branches are avoided.

REFERENCES:
patent: 4853840 (1989-08-01), Shibuya
patent: 5142634 (1992-08-01), Fite et al.
patent: 5511172 (1996-04-01), Kimura et al.
patent: 5522053 (1996-05-01), Yoshida et al.
patent: 5530825 (1996-06-01), Black
patent: 5537560 (1996-07-01), Boggs et al.
patent: 5634103 (1997-05-01), Dietz et al.
M. Johnson, "Supersealar Microprocessor Design", Prentice-Hall 1991, pp. 81-82.

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