Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-05-30
2002-06-04
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190
Reexamination Certificate
active
06400605
ABSTRACT:
BACKGROUND INFORMATION
1. Field of the Invention
The invention relates to integrated circuits, particularly to test and program modes in integrated circuit.
2. Description of Related Art
An integrated circuit undergoes verification and programming in program and test modes prior to release for shipment. The application of an external high voltage on one or more pins on a chip is a common approach to place a chip in test modes. For integrated circuits that are manufactured with a low pin count, a single pin may be designated with more than one function due to the limitation of the total pin count. This is particular true for pins that are assigned with test mode functions. Rather than dedicating a particular pin for usage solely during a program mode or test mode, that pin can be more widely utilized by placing another function on the same pin. Also in a conventional approach, on-chip programmable electrically erasable programmable read-only memory (EEPROM) bits are written with an internal charge pump for generating the programming voltage. However, the cost of an IC is increased with the additions of charge-pumps and high pin counts.
Accordingly, it is desirable to have a method and system for using a single pin of an IC that provides multiple functions during test modes.
SUMMARY OF THE INVENTION
The invention provides a single pin on an integrated circuit chip that serves multiple functions for placing the chip in test and program modes. A first predetermined high voltage level is applied to a test input pin to place the chip in test mode. A second predetermined high voltage level is applied to the test input pin to provide the programming voltage necessary to program a chip. Preferably, the integrated circuit is programmable that employs non-volatile memories with electrically erasable (E
2
) cells.
To preventing damage caused to internal circuits and the EEPROM, the incoming high-voltage from the test input pin is introduced gradually by a pulse shaping circuit. The pulse-shaping circuit provides a smooth transition when input voltage increases to the second predetermined high-level voltage.
The test input pin of the programmable chip connects to a first voltage level detector, a second voltage level detector, and a high-level switch. The first voltage sensor detects when the test input pin reaches a first predetermined voltage level. When the test input pin has reached the first predetermined voltage level, the programmable chip is in test mode. During the test mode, the programmable chip may interpret any combination of data or instructions differently than while operating under a normal mode. Sufficient gap between the first predetermined voltage level in test mode and the required voltage level in normal mode is necessary to prevent cross-over reading or writing data between the test and normal modes.
The second voltage level detector detects a second predetermined voltage level. Preferably, the second predetermined voltage level is set at a higher voltage level than the first predetermined voltage level. The function of the second voltage sensor is provide a programming voltage for storing information in a non-volatile EEPROM. When the second voltage sensor detects the test input pin near or at the second predetermined voltage level, a high-voltage pass gate is switched ON, placing the chip in program mode and allowing the programming voltage into the chip.
Advantageously, the use of the dual-level voltage sense and pulse-shaping circuits results in a smaller dimension of IC, with a lower pin count and smaller die size by eliminating a charge pump and related circuits. An integrated circuit that is programmable, such as employing electrical erasable cells, provides an advantage to program a chip after packing, as opposed to during the fabrication process at wafer level.
REFERENCES:
patent: 5856946 (1999-01-01), Chan et al.
patent: 5872733 (1999-02-01), Buti et al.
patent: 5963462 (1999-10-01), Engh et al.
patent: 6011715 (2000-01-01), Pasotti et al.
patent: 6034895 (2000-03-01), Naura et al.
Fernandez & Associates LLP
Phan Trong
Summit Microelectronics Inc.
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