Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-12-20
2002-08-20
Sherry, Michael J. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C324S073100
Reexamination Certificate
active
06437595
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more particularly to a method and system for allowing integrated circuits to be tested.
BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram of a conventional testing system
10
for bench testing, or DC testing, an integrated circuit
1
. The integrated circuit
1
includes pins
4
for electrically coupling the integrated circuit
1
to the conventional testing system
10
. In order to test the integrated circuit
1
, the integrated circuit
1
is coupled with a socket
20
. The pins
4
of the integrated circuit
1
are plugged into the socket
20
. The socket
20
is coupled with a switching box
30
. The switch box
30
includes a control panel
32
having knobs and dials. The switching box
30
includes relays (not explicitly shown) for connecting different pins with different parameter sources
34
,
36
,
38
,
40
,
42
and
44
. The parameter sources are preferably voltage sources.
FIG. 2
depicts a conventional method
50
for testing the integrated circuit
1
using the conventional testing system
10
. In order to test the integrated circuit
1
, an operator plugs the integrated circuit
1
into the socket
20
, via step
52
. An operator must then obtain the data book
12
for the conventional testing system
10
, via step
54
. The data book
12
indicates how to obtain a particular parameter from one of the parameter sources
34
,
36
,
38
,
40
,
42
and
44
for a particular pin of the integrated circuit
1
. Thus, the data book
12
indicates how the operator must set the knobs and dials for the control panel
32
in order to obtain the desired voltages for each of the pins on the integrated circuit
1
. The operator, therefore, reads and must understand the data book
12
, via step
56
. The operator then sets the knobs and dials on the control panel
32
in order to provide the desired parameters, typically voltages, to the socket
20
and, therefore, to the pins of the integrated circuit
1
. The operator then reads the result of the test and records the response, via step
60
. The operator then repeats steps
56
-
60
to complete testing of the integrated circuit, via step
62
.
Although the conventional method
50
and conventional system
10
are capable of testing the integrated circuit
1
, one of ordinary skill in the art will readily realize that the system
10
suffers from several drawbacks. The conventional system
10
and method
50
are difficult to use. In order to utilize the conventional system
10
, an operator must be able to read and understand the data book
12
. The operator must then be able to set the knobs and dials on the control panel
32
correctly. The operator must set the knobs and dials on the control panel
32
for a variety of parameters. For example, the operator must set the appropriate parameters for the DC bias, input leakage as well as open circuit and short circuit test parameters. This is difficult for an operator to do correctly and repeatably. The operator must also record the results of the testing. Although some conventional testing systems are capable of storing the resultants, the conventional system
10
typically has limited memory. Thus, the conventional system
10
typically has limited storage capacity. In addition, the conventional system typically utilizes a file format that is nontransferable. Thus, the resultant cannot be transferred to a computer system (not shown) for further analysis. In addition, the results cannot be easily incorporated into other documents and reports. Thus, both the setting of parameters and the recordation of results involve a great deal of manual work. This makes testing of the integrated circuit
1
prone to error. In addition, because so much is done manually, testing of the integrated circuit
1
using the conventional testing system
10
and the conventional method
50
is time consuming.
Accordingly, what is needed is a system and method for testing an integrated circuit
1
that is more efficient and less error prone. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for testing an integrated circuit using a plurality of parameters. The plurality of parameters are from a plurality of parameter sources. The integrated circuit includes a plurality of pins. The method and system comprise providing a signal converter, a controller coupled with the signal converter and a plurality of relays coupled with the controller. The signal converter is capable of being coupled with a computer system and is for converting between analog and digital signals. The signal converter receives values for the plurality of parameters from the computer and converts the values for the plurality of parameters to an analog signal indicating the values for the plurality of parameters. The controller is for receiving the analog signal indicating the values for the plurality of parameters from the signal converter and for providing at least one signal based on the analog signal indicating the values for the plurality of values. The plurality of relays is coupled with the integrated circuit and with the controller. The plurality of relays is for selectively coupling a portion of the plurality of pins of the integrated circuit with a portion of the plurality of parameter sources. The plurality of relays being controlled relays based on the at least one signal from the controller. The plurality of relays are thus controlled to provide the plurality of parameters from a portion of the plurality of parameter sources.
According to the system and method disclosed herein, the present invention provides an operator with the ability to test integrated circuits based on information entered into and possibly stored by the computer system. Thus, the complexity of testing of the integrated circuit is significantly reduced.
REFERENCES:
patent: 3597682 (1971-08-01), Hubbs
patent: 3854125 (1974-12-01), Ehling et al.
patent: 4656632 (1987-04-01), Jackson
patent: 4736374 (1988-04-01), Kump et al.
patent: 5388467 (1995-02-01), Jereb et al.
Boorananut Sedta
Fugdee Wirach
Mankhong Adunkitt
Nguyen Jimmy
Sawyer Law Group LLP
Sherry Michael J.
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