Method and system for providing adaptive timing recovery for...

Details Method and system for providing adaptive timing recovery for... Method and system for providing adaptive timing recovery for...

2007-04-03

2007-04-03

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Receivers

Angle modulation

C375S371000, C375S373000, C327S158000, C327S291000, C329S304000

Reexamination Certificate

active

10269795

ABSTRACT:
A system for providing adaptive timing recovery is provided. In an exemplary embodiment, the system includes a fractional resampler, an error function module and a loop filter, arranged collectively to form a timing recovery loop. In an initial mode, the error function module compares the output of the fractional resampler with a reference signal to determine an error, if any. An error signal is generated accordingly based on the error. The error signal is then provided to the loop filter allowing the loop filter to generate a correction signal. The correction signal is provided to the fractional resampler to allow the fractional resampler to generate an output which minimizes the error. When the error function module determines that the error is within an acceptable range, i.e., a timing lock is achieved, the system goes into a steady mode. In the steady mode, the error function module is directed to execute at a slower rate. By executing at a slower rate, the error function module is able to operate at a reduced level of power consumption.

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Kaenel et al, “A 320 MHZ, 1.5 mW@ 1.35 V CMOS PLL for Microprocessor Clock Generation”, IEEE Journal of Solid State Circuits, Nov. 1996, vol. 31, No. 11, p. 1715-1722.

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