Method and system for providing a single-instruction, multiple-d

Details Method and system for providing a single-instruction, multiple-d Method and system for providing a single-instruction, multiple-d

1994-09-28

1998-05-26

Shah, Alpesh M.

Pulse or digital communications

Repeaters

Testing

375375, 364230, 3642319, 3642613, 364DIG1, G06F 938

Patent

active

057581762

ABSTRACT:
A single-instruction, multiple-data (SIMD) execution unit for use in conjunction with a superscalar data processing system is provided. The SIMD execution unit is coupled to a branch execution unit within a superscalar processor. The branch execution unit fetches instructions from memory and dispatches vector processing instructions to the SIMD execution unit via the instruction bus. The SIMD execution unit includes a control unit and a plurality of processing elements for performing arithmetic operations. The processing elements further include a register file having multiple registers and an arithmetic logic unit coupled to the register file. The arithmetic logic unit may include a fixed-point unit for performing fixed-point vector calculations and a floating-point unit for performing floating-point vector calculations. Once the control unit within the SIMD execution unit receives a vector instruction, the control unit translates the instruction into commands for execution by selected processing elements within the SIMD execution unit. If such a vector instruction requires access to memory, a fixed point execution unit within the superscalar processor may be utilized to calculate a memory address which is then utilized by the SIMD execution unit to access memory.

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patent: 5197137 (1993-03-01), Kumar et al.
patent: 5442760 (1995-08-01), Rustad et al.
patent: 5465373 (1995-11-01), Kahle et al.

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