Etching a substrate: processes – Nongaseous phase etching of substrate
Reexamination Certificate
1998-12-09
2001-06-05
Chaudhari, Chandra (Department: 2813)
Etching a substrate: processes
Nongaseous phase etching of substrate
C216S038000, C216S056000, C156S345420
Reexamination Certificate
active
06241907
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to detection of faults in semiconductor devices and more particularly to a method and system for providing a package to facilitate decapsulation of a chip-scale package.
BACKGROUND OF THE INVENTION
Chip-scale packages are increasingly used in semiconductor applications. Chip-scale packages are so named because of their size. The entire package is on the order of the size of the semiconductor die, or chip, within the package. Typically, a chip scale package includes a substrate to which the semiconductor die is attached. The semiconductor die is typically attached to one side of the substrate and encapsulated in an epoxy molding compound. The substrate typically includes a plurality of conductive traces which run through the substrate, electrically coupling the semiconductor die to solder balls. The solder balls are typically on the opposite side of the substrate as the semiconductor die. The solder balls are used to electrically couple the chip-scale package to an external system board.
In order to determine if semiconductor devices are being designed and manufactured properly, it is often desirable to deprocess the semiconductor devices. In larger, conventional packages, the package is mounted on an apparatus. Typically, the edges of the package are used to hold the package. The plastic molding compound is then removed from the top surface of the die by chemical etching, exposing the semiconductor die. The semiconductor die can then be examined and diagnosed when exposed. Additional layers of the semiconductor die can also be removed to further examine and diagnose the semiconductor die. Thus, the package is decapsulated and the functionality of the semiconductor die checked.
For similar reasons, it is also desirable to decapsulate chip-scale packages. In order to decapulate a chip-scale package in a conventional manner, the edges of the chip-scale packages are used to hold the package in place during decapsulating. Layers of the chip-scale package are then removed. For example, a portion of the encapsulant may be etched to expose the semiconductor die. The semiconductor die is then tested.
Although conventional methods for decapsulating the chip-scale package can provide information relating to the chip-scale package, much of the chip-scale package cannot be decapsulated using the conventional method. The chip-scale package is on the order of the same size as the semiconductor die. Thus, when the edges of the chip-scale package are used to hold the chip-scale package in place, a portion of the semiconductor die remains covered. As a result, only the central portion of the semiconductor die is typically exposed and tested. The periphery of the semiconductor die remains intact. For example, bond pads for connecting the semiconductor die to the substrate usually are near the periphery of the semiconductor die. Consequently, the bond pads may not be tested. In the alternative, if the edges of the chip-scale package are exposed for etching, then chemicals used to etch the encapsulant may run down the sides of the chip-scale package. Thus, the substrate may be etched instead of the molding compound. Consequently, the desired portion of the semiconductor die may not be exposed.
Accordingly, what is needed is a system and method for providing a method for decapsulating a chip-scale package. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for decapsulating a chip-scale package having a first width. The method and system comprise coupling the chip-scale package to a substantially rigid receptacle. The receptacle has a second width and a periphery. The second width is larger than the first width. The chip-scale package does not extend to the periphery of the receptacle. The method and system further comprise holding the receptacle in proximity to the periphery and decapsulating the chip-scale package.
According to the system and method disclosed herein, the present invention allows for chip-scale packages to be better decapsulated, thereby increasing overall system performance.
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Gannamani Ranjit
Li Xia
Advanced Micro Devices , Inc.
Chaudhari Chandra
Sawyer Law Group LLP
Schillinger Laura M
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