Boots – shoes – and leggings
Patent
1992-02-21
1995-03-14
Trans, Vincent N.
Boots, shoes, and leggings
364488, 364489, 364490, G06F 1560
Patent
active
053981952
ABSTRACT:
A floor planning technique is provided herein wherein an initial floor plan having a predefined area and a number of overlapping modules is used to produce a final floor plan having the same predefined area and no overlapping modules. In order to eliminate the overlaps, a two stage process is performed. The first stage includes minimizing the overlaps by performing a series of move and/or reshape operations on the overlapping modules. The amount an overlapping module is moved and/or reshaped is based upon a computed net repelling force. After the move and/or reshape operations no longer minimize overlaps, the second stage is performed. The second stage, referred to as fitting, fits each overlapping module into the predefined area by awarding the overlapping area to the module or protruding the overlapping module into available space surrounding the module. The space that a module extends into is determined by calculating attracting forces. Once the second stage is complete, the resulting floor plan is legal having no overlapping modules.
REFERENCES:
patent: 4554625 (1985-11-01), Otten
patent: 4593363 (1986-06-01), Burstein et al.
patent: 4630219 (1986-12-01), DiGiacomo et al.
patent: 4791586 (1988-12-01), Maeda et al.
patent: 4805113 (1989-02-01), Ishii et al.
patent: 4829446 (1989-05-01), Draney
patent: 4872103 (1989-10-01), Kingsley
patent: 4918614 (1990-04-01), Modarres et al.
patent: 5047949 (1991-09-01), Yamaguchi et al.
patent: 5050091 (1991-09-01), Rubin
patent: 5062054 (1991-10-01), Kawakami et al.
patent: 5140402 (1992-08-01), Murakata
patent: 5191542 (1993-03-01), Murofushi
patent: 5224056 (1993-06-01), Chene et al.
"Floor Planning and Global Routing in an Automated Chip Design System", by Yu-Chin Hsu, Report No. UIUCDCS-R-87-1353, Computer Science Thesis, University of Illinois; (1987).
"Overlap Resolution Problem for Block Placement in VLSI Layout", Ohmura, et al, Electronics and Communications in Japan, Part 3, vol. 72, No. 6 (1990) pp. 68-76.
"A Block Placement Procedure Using a Force Model", Onodera, et al, Electronics and Communications in Japan, Part 3, vol. 72, No. 11, (1989) pp. 87-96.
"CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design", Ueda, et al, IEEE Transactions on Computer-Aided Design, vol. CAD-4, No. 1, (Jan. 1985) pp. 12-22.
"New Algorithms for the Rectilinear Steiner Tree Problem", Ho, et al, IEEE Transactions on Computer-Aided Design, vol. 9, No. 2, (Feb. 1990) pp. 185-193.
"Algorithm for VLSI Chip Floor Plan", Ueda, et al, Electronics Letters, vol. 19, No. 3, (Feb. 1983) (pp. 77-78).
Garbowski Leigh Marie
International Business Machines - Corporation
Trans Vincent N.
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