Method and system for providing a codec clock signal at a...

Pulse or digital communications – Receivers – Automatic gain control

Reexamination Certificate

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Details

C370S352000, C345S211000, C713S324000, C713S503000

Reexamination Certificate

active

10144295

ABSTRACT:
A clock generator system and method for providing and operating a codes with a clock signal at a desired operational rate are disclosed. The clock generator system also has a phase-locked loop circuit. The clock generator system determines whether an available clock signal within a circuit environment of the codec has a desired clock rate. If the available clock signal has the desired clock rate, the clock generator system supplies and operates the codec with the available clock signal. If the available clock signal does not have the desired clock rate, the phase-locked loop circuit generates from the available clock signal a desired clock signal having the desired clock rate and supplies and operates the codec with the desired clock signal.

REFERENCES:
patent: 5512938 (1996-04-01), Ohno
patent: 6347380 (2002-02-01), Chang et al.
patent: 6980056 (2005-12-01), Alexander et al.
patent: 7003682 (2006-02-01), Irazabal et al.
patent: 2002/0172189 (2002-11-01), Lazarus et al.
patent: 2003/0016066 (2003-01-01), Irazabal et al.
patent: 2003/0025689 (2003-02-01), Kim

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