Method and system for protecting a stacked gate edge in a semi-c

Details Method and system for protecting a stacked gate edge in a semi-c Method and system for protecting a stacked gate edge in a semi-c

1995-06-01

1996-05-14

Fears, Terrell W.

Static information storage and retrieval

Format or disposition of elements

365 53, 365182, G11C 1300

Patent

active

055174434

ABSTRACT:
A process for protecting the stacked gate edge of a semiconductor device is disclosed. The process provides for providing a spacer formation before the self aligned source (SAS) etch is accomplished. By providing the spacer formation prior to the SAS etch, tunnel oxide integrity is much improved and the source junction implant profile is much more uniform because the silicon around the source region is not gouged away.

REFERENCES:
patent: 5053848 (1991-10-01), Houston et al.

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