Method and system for programmable pipelined graphics...

Details Method and system for programmable pipelined graphics... Method and system for programmable pipelined graphics...

2005-09-20

2005-09-20

Bella, Matthew C. (Department: 2676)

Computer graphics processing and selective visual display system

Computer graphic processing system

C345S502000, C345S503000, C345S504000, C345S505000, C345S506000, C712S229000

Reexamination Certificate

active

06947047

ABSTRACT:
A programmable, pipelined graphics processor (e.g., a vertex processor) having at least two processing pipelines, a graphics processing system including such a processor, and a pipelined graphics data processing method allowing parallel processing and also handling branching instructions and preventing conflicts among pipelines. Preferably, each pipeline processes data in accordance with a program including by executing branch instructions, and the processor is operable in any one of a parallel processing mode in which at least two data values to be processed in parallel in accordance with the same program are launched simultaneously into multiple pipelines, and a serialized mode in which only one pipeline at a time receives input data values to be processed in accordance with the program (and operation of each other pipeline is frozen). During parallel processing mode operation, mode control circuitry recognizes and resolves branch instructions to be executed (before processing of data in accordance with each branch instruction starts) and causes the processor to operate in the serialized mode when (and preferably only for as long as) necessary to prevent any conflict between the pipelines due to branching. In other embodiments, the processor is operable in any one of a parallel processing mode and a limited serialized mode in which operation of each of a sequence of pipelines (or pipeline sets) pauses for a limited number of clock cycles. The processor enters the limited serialized mode in response to detecting a conflict-causing instruction that could cause a conflict between resources shared by the pipelines during parallel processing mode operation.

REFERENCES:
patent: 6088044 (2000-07-01), Kwok et al.
patent: 6198488 (2001-03-01), Lindholm et al.
patent: 6243107 (2001-06-01), Valtin et al.
patent: 6279100 (2001-08-01), Tremblay et al.

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