Method and system for producing a synchronous signal from _cycli

Pulse or digital communications – Spread spectrum – Direct sequence

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Details

371 42, 371 69, 370105, H04L 108, H04L 708

Patent

active

044816480

ABSTRACT:
Each block of data having information data and redundant bits is transmitted without any synchronous signal bit word, while transmitted data is processed to find the boundary between consecutive data blocks so that a synchronous signal will be produced at the receiving end. The system for producing the synchronous signal comprises a cyclic redundancy check (CRC) circuit, a frequency divider for dividing the frequency of shift clock pulses and a reset pulse generating circuit. The reset pulse generating circuit is responsive to the output signal from the frequency divider and the shift clock pulses to produce periodically first and second reset pulses with which the CRC circuit and the frequency divider are initialized. The reset pulse generating circuit is further responsive to an error signal from the CRC circuit so that further first and second reset pulses are produced with which the CRC circuit and the frequency divider are initialized again. Initialization is repeated until the frequency divider is synchronous with the bits of the data blocks, and once synchronizm is established, the output signal from the frequency divider can be regarded as the synchronous signal indicative of the boundary between any two consecutive data blocks.

REFERENCES:
patent: 3789359 (1974-01-01), Clark, Jr. et al.
patent: 4375102 (1983-02-01), VanDaal

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