Method and system for processing integrated circuits

Details Method and system for processing integrated circuits Method and system for processing integrated circuits

1999-03-22

2002-06-04

Nguyen, Vinh P. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010

Reexamination Certificate

active

06400171

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention generally relates to semiconductor integrated circuits, and more particularly, the invention relates to procedures for detecting defects and faults in such circuits.
Integrated circuits typically incorporate a very high density of circuit components, most of which are susceptible to a variety of faults and physical defects. Many of these faults arise during manufacture of the integrated circuits. For this reason, it is necessary to test these circuits, and a variety of tests are known and used.
One technique commonly used to detect circuit faults in Complementary Metal Oxide Semiconductor (CMOS) integrated circuits is a procedure referred to as the IDD current test or the IDDQ test. This test attempts to measure the quiescent current of a chip between supply voltage, VDD, and ground potential GND. Generally, IDDQ testing is based upon the fact that absent any internal faults, the quiescent VDD supply current in a typical CMOS integrated circuit is on the order of less than 100 nanoamps. A physical defect such as bridging will produce a measurable increase in quiescent supply current. With IDDQ testing, a high level of defect coverage can be obtained with a minimal test time.
To help detect defects in chips with high resistance caused leakage problems, a procedure referred to as burn-in is often used as an acceleration technique. Burn-in is a method used to accelerate failures in a device if there is a weak feature or defect that is sensitive to extended operation of the device. Defects such as weak oxides, narrow silicon or metal lines, small resistive contacts, or other similar flaws usually become more apparent with burn-in and are therefore more readily identified during testing.
One of the main problems facing product burn-in is the high standby IDDQ current. Any circuit with known high source of IDD current such as bipolar circuit or FETS with high off current will mask defect-induced current and/or lower chip burn-in throughput. For example, at burn-in conditions, the FET off currents increase significantly due to lower threshold voltages (Vt) at high temperature, resulting in high IDDQ. Unless these currents can be kept reasonably low, burn-in is less effective and more expensive. Prior art efforts to address this problem have several drawbacks. For example, with one approach, an external control signal has to be applied and chip space is taken for global wiring and external pins.
SUMMARY OF THE INVENTION
An object of this invention is to reduce high currents that are not defect-related during burn-in of a CMOS integrated circuit.
Another object of the present invention is to provide a procedure for reducing currents during burn-in of a CMOS integrated circuit that does not require any external pin on the chip or any external control signal applied to the chip.
Another object of the present invention is to provide a procedure for reducing noise generation or increasing noise immunity of circuits during burn-in.
Another object of the present invention is to use an on-chip circuit to reduce currents during burn-in of a CMOS integrate circuit.
These and other objectives are attained with a circuit and a method for automatically detecting an operating condition of an integrated circuit chip and for automatically outputting a control signal in response to automatically detecting one of at least two said operating conditions.
With the preferred embodiment of the invention, FET off currents are reduced during burn-in of a CMOS integrated chip. This is done by a compact, local sensing circuit. The sensing circuit is off during the normal chip operation, and the sensing circuit is only used where needed to provide a local signal to cut down excessive FET off currents.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.


REFERENCES:
patent: 4743841 (1988-05-01), Takeuchi
patent: 5294883 (1994-03-01), Akiki et al.
patent: 5349290 (1994-09-01), Yamada
patent: 5448199 (1995-09-01), Park
patent: 5497117 (1996-03-01), Nakajima et al.
patent: 5570034 (1996-10-01), Needham et al.
patent: 5644251 (1997-07-01), Colwell et al.
patent: 5652524 (1997-07-01), Jennion et al.
patent: 5670890 (1997-09-01), Colwell et al.
patent: 5721495 (1998-02-01), Jennion et al.
patent: 5732032 (1998-03-01), Park et al.
patent: 5745499 (1998-04-01), Ong

Affiliated with

Also associated with

Rating

Method and system for processing integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for processing integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for processing integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2931279