Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-07-16
2003-11-04
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C713S324000
Reexamination Certificate
active
06642879
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to an analog-to-digital converter, and, in particular, to a serial interface controller of a serial data interface for an analog-to-digital (“A/D”) converter. Still more particularly, the present invention relates to a method and system for powering down an analog-to-digital converter into a sleep mode.
2. Description of the Related Art
Analog-to-digital converters (“ADCs”) are used to convert an analog signal to a digital signal for digital processing and/or storage. ADCs are well known in the art and are used in a variety of applications. An ADC generally has an analog system and a digital system coupled to each other. The analog system includes at least a modulator for modulating the input analog signal. The analog system processes and converts an analog input signal to a digital output signal. The digital system processes and outputs the digital signal. The digital system typically has a digital logic system, a clock generator, a filter, and a serial port block coupled to each other. The filter operates to remove and/or reduce unwanted parts of the digital signal. The serial port block further has a serial data interface with a serial interface controller, which allows a serial device to be coupled to and communicate with the ADC.
Applications of the ADC may require acquiring data by taking samples or readings (e.g., monitoring of temperature or weight readings). Some applications require the taking of continuous samples or readings by a device interfaced with the serial port block, and the ADC continuously converts data in providing the samples or readings to be outputted to the interfaced device. Other applications require the taking of a single or few samples/readings at a time. In these applications, the user utilizes the interfaced device to read the converted data from the digital system of the ADC only some or part of the time (e.g., as the user requests the need for the data). The ADC, however, continuously converts input signals whether or not they are utilized or retrieved by the user through the interfaced device. As the ADC continuously converts input signals, the ADC continuously consumes power.
The present invention recognizes the need and desire to minimize or reduce the power consumption by an ADC when possible. Reduced or minimized power consumption for electronic devices or components, such as handheld or portable electronic devices, is a generally desired goal in saving overall power. One way of reducing or minimizing power would be to shut down the power supply for the ADC. Shutting down the power supply for the ADC poses various problems. One problem is that the power supply may be desired or needed to maintain at least some of the components of the ADC in a powered-on mode. Shutting down the power supply would entirely shut down all components of the ADC. Another problem is that after shut down of the power supply, the power supply needs to start up again, and various start-up problems may result. For example, the power supply for the ADC may require an elapsed time period before fully powering back on, and the ADC may not be able to timely power on again to take appropriate readings or samples by the interfaced device and/or user.
Also, configurations exist in which multiple chips are connected to the same power supply. In these configurations, all of the chips connected to the power supply would have to be powered down if the power supply were shut down. If one chip among the multiple chips has to stay powered on, then the remaining chips also have to stay on. Therefore, there is a need and desire to develop a system and/or way of selectively powering down each chip among the multiple chips connected to the same power source.
An extra pin for the ADC chip may be needed for switching between powering down and powering up the ADC chip. For example, this extra pin would be set to a high value to power down the ADC chip and set to a low value to power up the ADC chip. However, the present invention also recognizes the need and desire to minimize or reduce the number of pins on an ADC chip. Extra pins add to the space and cost of the ADC chip.
The present invention recognizes the desire or need for an ADC, which is able to power down when conversions and/or converted data are not desired or needed to be read or sampled by a user through an interfaced device. Furthermore, the present invention also recognizes the desire or need to not add an extra pin for controlling the power-down and power-up modes of the ADC. The present invention overcomes the problems and disadvantages in accordance with the prior art.
SUMMARY OF THE INVENTION
A method and system for powering down an analog-to-digital converter (“ADC”) into a sleep mode are disclosed. If the ADC receives a normal set of pulses for a serial clock signal of the ADC, a serial interface controller outputs converted data requested by a user through a serial interface. Also, if the ADC receives a sleep set of pulses for the serial clock signal, a state machine of the ADC powers down the ADC into a sleep mode in which at least parts of the ADC are operated at a reduced power consumption level. Furthermore, if the ADC is in the sleep mode and the ADC receives a wake-up set of pulses for the serial clock signal, the state machine powers back up the ADC from the sleep mode.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5294928 (1994-03-01), Cooper et al.
patent: 5422807 (1995-06-01), Mitra et al.
patent: 5619204 (1997-04-01), Byrne et al.
patent: 5714955 (1998-02-01), Reay et al.
patent: 5886658 (1999-03-01), Amar et al.
patent: 5914681 (1999-06-01), Rundel
patent: 6057795 (2000-05-01), Suzuki
patent: 6070140 (2000-05-01), Tran
patent: 6072417 (2000-06-01), Staton
patent: 6163851 (2000-12-01), Yamazoe et al.
Amar Aryesh
Steiner Philip
Cirrus Logic Inc.
Jeanpierre Peguy
Lin, Esq. Steven
LandOfFree
Method and system for powering down an analog-to-digital... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for powering down an analog-to-digital..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for powering down an analog-to-digital... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3142200