Method and system for power conservation in memory devices

Details Method and system for power conservation in memory devices Method and system for power conservation in memory devices

2003-03-18

2004-05-04

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Powering

Data preservation

C365S227000, C365S203000

Reexamination Certificate

active

06731564

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to semiconductor devices and more particularly to a method and system for power conservation in memory devices.
BACKGROUND OF THE INVENTION
Many electronic devices in today's society utilize static random access memory (“SRAM”), which is a memory that loses its data upon loss of normal operating power. Many devices using SRAM are designed to be portable, which requires the use of a battery as a power source. One limitation for such portable devices is the life of the battery. To prolong the life of the battery while preserving the data stored in the SRAM, many portable devices are capable of shutting down normal operating power while continuing to provide a lower voltage for the SRAM for data maintenance. This is commonly referred to as a standby mode. An example of a device operable to assume a standby mode is a cellular phone.
A problem with such an approach is that leakage of direct current occurs during the standby mode, which may drain the battery power after a certain amount of time. Thus, the portability of the device may be limited due to the need to recharge or replace the battery.
SUMMARY OF THE INVENTION
According to one embodiment of the invention, a memory circuit operable to assume a standby mode is provided. A memory circuit includes a transistor comprising a gate and a bulk. The bulk is at a retention voltage level. The memory circuit also includes a first node and a second node that are coupled to each other by the transistor. The first node is operable to assume a higher voltage level than the second node in response to an initiation of the standby mode. The memory circuit also includes a third node coupled to the gate of the transistor. The third node is operable to assume a voltage approximately equal to the retention voltage in response to an initiation of the standby mode. The transistor is operable to reduce any direct current flow between the first node and the second node in response to a rise in voltage at the third node to a voltage approximately equal to the retention voltage.
Some embodiments of the invention provide numerous technical advantages. Some embodiments may benefit from some, none, or all of these advantages. For example, according to one embodiment, the battery life of an electronic device is prolonged by blocking the leakage current flowing from its memory circuit while the device is in a standby mode. According to another embodiment, gate leakage is minimized by adjusting the level of voltage applied to the gate of a transistor that is blocking the leakage current. According to another embodiment, the number of components required to minimize the level of current leakage is reduced by minimizing the number of leakage paths.
Other technical advantages may be readily accertained by one of skill in the art.


REFERENCES:
patent: 4796227 (1989-01-01), Lyon et al.
patent: 6343045 (2002-01-01), Shau

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