Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Analysis and verification
Reexamination Certificate
2008-05-29
2011-10-11
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Analysis and verification
C716S052000
Reexamination Certificate
active
08037428
ABSTRACT:
One embodiment of the present invention provides a system that verifies an integrated circuit (IC) chip layout. During operation, the system receives a layout of an IC chip after the layout has gone through a place-and-route operation. Next, the system performs a lithography compliance checking (LCC) operation on the layout to detect lithography hotspots within the layout, wherein each lithography hotspot is associated with a local routing pattern around the lithography hotspot. Next, for each detected lithography hotspot, the system compares the associated local routing pattern against a hotspot database to determine if the local routing pattern matches an entry in the hotspot database, which stores a set of known hotspot configurations. If so, the system corrects the lithography hotspot using correction guidance information associated with the hotspot configuration stored in the hotspot database. Otherwise, the system corrects the lithography hotspot by performing a local rip-up and reroute on the local routing pattern, iteratively, until achieving convergence or given number of iterations.
REFERENCES:
patent: 6189131 (2001-02-01), Graef et al.
patent: 7240305 (2007-07-01), Lippincott
patent: 7861203 (2010-12-01), White et al.
Miloslavsky Alex
Tang Zongwu
Tong Yang-Shan
Tseng Wei-Chih
Wei Linni
Chiang Jack
Park Vaughan Fleming & Dowler LLP
Synopsys Inc.
Tat Binh
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