Method and system for placement of electric circuit...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing

Reexamination Certificate

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C716S122000, C716S126000

Reexamination Certificate

active

08010925

ABSTRACT:
The invention relates to a method and a system for placing electric circuits in integrated circuit chip design. Specifically, the invention encompasses performing a global placement step placing the cells into bins on the chip, as well as a detailed placement process which arranges the cells in the bins to obtain a legal arrangement while generating simply connected free space for routing channels.

REFERENCES:
patent: 6068662 (2000-05-01), Scepanovic et al.
patent: 6904584 (2005-06-01), Brenner et al.
patent: 2001/0010090 (2001-07-01), Boyle et al.
patent: 2003/0217338 (2003-11-01), Holmes et al.

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