Method and system for pipelined processing in an integrated...

Details Method and system for pipelined processing in an integrated... Method and system for pipelined processing in an integrated...

2010-07-20

2011-11-29

Couso, Jose (Department: 2624)

Image analysis

Image compression or coding

Parallel coding architecture

Reexamination Certificate

active

08068681

ABSTRACT:
A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data.

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Bolton et al., “A Complete Single-Chip Implementation of the JPEG Image Compression Standard”. Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, May 1991, San Diego, CA, pp. 12.2.1-12.2.4.

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