Method and system for performing ternary verification

Details Method and system for performing ternary verification Method and system for performing ternary verification

2007-02-16

2010-06-08

Phan, Thai (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Modeling by mathematical expression

C703S014000, C716S030000, C716S030000, C714S741000

Reexamination Certificate

active

07734452

ABSTRACT:
A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary model are then recorded. Next, the number of the recorded gate pairings is reduced by removing all invalid gate pairings. A ternary verification is performed on the ternary model having a reduced number of gate pairings.

REFERENCES:
patent: 5377201 (1994-12-01), Chakradhar et al.
patent: 5649165 (1997-07-01), Jain et al.
patent: 5657240 (1997-08-01), Chakradhar et al.

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