Method and system for performing parallel integer multiply...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S513000

Reexamination Certificate

active

07043518

ABSTRACT:
A multiply accumulate unit (“MAC”) that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation, each contain either four 8-bit operands, two 16-bit operands, or one 32-bit operand. Depending on the mode of operation, the MAC performs either sixteen 8×8 operations, four 16×16 operations, or one 32×32 operation. Results may be individually retrieved from registers and the corresponding accumulator cleared after the read cycle. In addition, the accumulators may be globally initialized. Two results from the 8×8 operations may be packed into a single 32-bit register. The MAC may also shift and saturate the products as required.

REFERENCES:
patent: 6230180 (2001-05-01), Mohamed
patent: 6282556 (2001-08-01), Chehrazi et al.
patent: 6385634 (2002-05-01), Peleg et al.
patent: 6611856 (2003-08-01), Liao et al.
patent: 2003/0097391 (2003-05-01), Saulsbury
Paper: Nathan Slingerland et al., “Performance Analysis of Instruction Set Architecture Extensions for Multimedia”, 23 pages.

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