Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2008-09-30
2011-12-27
Whitmore, Stacy (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
Reexamination Certificate
active
08086983
ABSTRACT:
A method, system, and computer program product are disclosed for performing crosstalk analysis using first-order parameterized analysis modeling. The approach can be used to factor in the effect of process variations within the definition of timing windows. This approach allows one to bypass the simplistic assumptions related to best-case/worst-case analysis using timing windows, and provide a realistic picture of the impact of timing windows on noise analysis. The timing windows can be viewed in terms of the individual process parameter. The process parameters could be real process parameters, or virtual/computed components based on the actual process parameters. The process parameters can be used to compute overlap of timing windows for performing noise analysis.
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Parameswaran Harindranath
Shrivastava Sachin
Cadence Design Systems Inc.
Vista IP Law Group LLP
Whitmore Stacy
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