Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
2007-10-02
2007-10-02
McElheny, Jr., Donald E. (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C703S014000
Reexamination Certificate
active
11134803
ABSTRACT:
A method, mechanism, and system for determining an effective resistance for a network of resistors, irrespective of the number of terminals is provided. An aspect of an approach relates to the reduction of any network of resistors to a single resistance value. Another aspect of an approach relates to the application of a power loss calculation to determine the effective resistance. Yet another aspect of an approach relates to the integration of the method/mechanism with an analog simulator.
REFERENCES:
patent: 5943487 (1999-08-01), Messerman et al.
patent: 6897761 (2005-05-01), Ernsberger et al.
patent: 6978214 (2005-12-01), Budell et al.
patent: 7039888 (2006-05-01), Steinmann et al.
Glez Harbour et al., Calculation of Multiterminal Resistances in Integrated Circuits, 1986 IEEE Transactions on Circuits and Systems, vol. CAS-33, No. 4, pp. 462-465.
Zhao et al., Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-micron CMOS Circuits, 2000 IEEE, pp. 65-72.
Stark et al., Techniques for Calculating Currents and Voltages in VLSI Power Supply Networks, Feb. 1990 IEEE Transactions on Computer-Aided Design, vol. 9, No. 2, pp. 126-132.
Cadence “Parasitic Simulation User Guide” Product 4.4.6, Jun. 2003, Cadence Design Systems, Inc., USA.
Cadence “Ultrasim User Guide” Product Version 3.3, Oct. 2003, Cadence Design Systems, Inc., USA.
O'Brien, P.R. et al. “Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimations” Proceedings of the 1989 IEEE International Conference on Computer-Aided Design (ICCAD-89), Nov. 5-9, 1989, pp. 512-516.
Rao, V. et al. “Aggressive Crunching of Extracted RC Netlists”, Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, CA, 2002, pp. 70-77.
Rao, V. et al. “Aggressive Crunching of Extracted RC Netlists”, 2002, pp. 1-32, located at www.tauworkshop.com/TauSlides/4.5.ppt.
Sheehan, B.N. “TICER: Realizable Reduction of Extracted RC Circuits” Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design (ICCAD'99), San Jose, CA, 1999, pp. 1-4.
Dennison Ian
Dennison Keith
Gebbie Ian
Haag Zsolt
Bingham Mccutchen LLP
Cadence Design Systems Inc.
Le Toan M.
McElheny Jr. Donald E.
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