Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Software program
Reexamination Certificate
1999-03-26
2003-10-07
Broda, Samuel (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Software program
C702S117000, C716S030000, C714S728000, C714S738000, C714S741000
Reexamination Certificate
active
06631344
ABSTRACT:
FIELD OF THE INVENTION
The field of the present invention pertains to the testing of integrated circuits. More particularly, the present invention pertains to a method and system for efficiently generating test vectors for use with automated testing equipment (ATE) for testing integrated circuits to detect faults therein.
BACKGROUND OF THE INVENTION
Computer systems, software applications, and the devices and processes built around them are continually growing in power and complexity. Society's reliance on such systems is likewise increasing, making it critical that the systems obey the properties their designers intended. Typically, the more powerful and complex the system, the greater its utility and usefulness. However, as these computer and software implemented systems and processes become more powerful, detecting and correcting flaws within the systems becomes increasingly difficult.
As integrated circuits, and particularly the logic portion of integrated circuits, have become more complex and more dense, they have become progressively harder to test in order to ensure correct and complete functionality. For example, with current technology, as the total number of transistors fabricated within an integrate circuit die increases, the amount of time which the integrated circuit emerging from a fabrication process line spends in testing increases as well.
The most modern integrate circuit devices are achieving greater and greater densities. The higher densities are greatly increasing the costs associated with devising sufficiently accurate tests which adequately ensure the complete functionality of the most sophisticated devices. Higher densities are achieved in part by reducing the amount of space between transistors and other components which comprise the integrated circuit. As such, the “place and route” tolerances for the integrate circuit are reduced, and the potential for introducing errors and introducing structural faults in the circuit itself increases. Additionally, the complicated placement of the internal structure and nature of the faults encountered in such high density integrated circuits requires the use of sophisticated algorithms in order to ensure adequate error detection (e.g., being able to determine whether structural faults between the closely spaced gate elements, such as a bit short, broken link, or the like, exist). Hence, the testing cost can be very significant for the latest and largest high density integrated circuits. Very sophisticated test programs, automatic test pattern generation (ATPG) programs, are used to analyze the various netlists representative of the integrated circuit designs and generate therefrom the test patterns (e.g., also referred to as test programs or test vectors) used for testing the devices in ATE systems.
As is well known, a typical integrated circuit has two categories of faults, commonly referred to as “easy faults” and “hard faults”. Easy faults are categorized as those faults that can be detected by a large number of different test programs, or “test vectors”. Easy faults tend to have relatively few inputs required in order to generate the characteristic output from the integrate circuit which indicates the presence of the fault. Hard faults are characterized as those faults which are detectable by very few test vectors. Hard faults tend to have large numbers of inputs, each of which must be correct, required in order to create a difference in the operation of the good and faulty circuit at an output to indicate the presence of a fault.
Thus, as should be noted by the above definition, a randomly generated test vector would likely detect at least one or more easy faults but very few, if any, hard faults. The effort spent in generating a random test pattern is much less than the effort expended in the deterministic counterpart; the deliberate stepwise generation of the precisely targeted deterministic test pattern. Accordingly, automatic test pattern generation for detecting easy faults is a much more straightforward process then test pattern generation for detecting the hard faults. With very high density integrated circuits, using deterministic test pattern generation to obtain near complete coverage of the design is very expensive (e.g., extremely compute intensive).
The objective of the automatic test pattern generation program is to generate an accurate, high coverage test pattern as efficiently as possible, to reduce the cost. Accordingly, most prior art automatic test pattern generation programs are configured to utilize a random pattern generation phase before using a deterministic test generation phase. The intent of this scheme is to minimize the cumulative computer system run-time required for generating a precise end-to-end deterministic test pattern.
Prior art automatic test pattern generation programs proceed through a random test vector generation phase in order to provide for the detection of easy faults. The random phase is followed by a deterministic phase, wherein the program deliberately and deterministically generates test vectors for detecting each of the remaining faults, e.g., the hard faults.
The problem with this approach, is the fact that even though the automatic test pattern generation program uses relatively fast random test pattern generation in its first phase, the second deterministic phase still requires an inordinate amount of processing time. Each hard fault requires a full deterministic analysis of the logic circuitry to determine a test pattern capable of revealing the presence of the hard fault. Generating test patterns for detecting all of the hard faults can thus be very expensive.
Thus, what is required is an automatic test pattern generation program capable of generating a test vector in much less time than the prior art. What is required is an algorithm for generating test vectors which is much more efficient than the prior art algorithms. The required solution should be capable of quickly generating test patterns for detecting easy faults. Additionally the required solution should be capable of generating test patterns for detecting each of the remaining hard faults in less time than the prior art.
SUMMARY OF THE INVENTION
The present invention provides an automatic test pattern generation program capable of generating a test vector in much less time than the prior art the present invention provides an algorithm for generating test vectors which is much more efficient than the prior art algorithms. The present invention provides a method and system capable of quickly generating test patterns for detecting easy faults, and a method and system for generating test patterns for detecting each of the remaining hard faults in less time than the prior art.
In one embodiment, the present invention is implemented as an ATPG process executing within a CAD workstation. The ATPG process uses a speculative algorithm to efficiently generate test vectors for an integrated circuit. The test vectors are subsequently used with ATE (automated test equipment). The speculative process (at times referred to as speculative ATPG) includes the computer implemented steps of receiving a netlist specification representing the design of the integrated circuit in the RAM of the CAD workstation, and processing and simulating the netlist. Using the instantiated simulation, random test pattern generation is used to obtain the test vectors for the easy faults. Then, for each remaining hard fault, deterministic test pattern generation is performed to obtain a portion of the test vector. The test vector created as a result of this step is a partial solution of the complete deterministic test pattern generation process. Random analysis is then performed to obtain a remaining portion of the test vector. The partial deterministic portion and the remaining randomly generated portion comprise an entire test vector operable to detect the fault when used with the ATE.
In so doing, the present invention leverages the fact that random analysis is more efficient, less expensive, and much faster than determinist
Kapur Rohit
Williams Thomas W.
Bever Hoffman & Harms LLP
Broda Samuel
Harms Jeanette S.
Synopsys Inc.
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