Method and system for optimizing a transistor model

Details Method and system for optimizing a transistor model Method and system for optimizing a transistor model

1993-04-13

1995-06-13

Cosimano, Edward R.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

054249643

ABSTRACT:
A modeling system 10 comprises a central processing unit 12 coupled to an arithmetic logic unit 16. A device testing system 18 is used to empirically analyze the operational characteristics of a transistor to be modeled by the system 10. A set of parameter values are stored in a memory circuit 14 coupled to central processing unit 12. An input and display system 20 is used to interact with the central processing unit 12. The central processing unit 12 uses the arithmetic logic unit 16 to calculate an objective function which is essentially a measure of the error between the measured values of operating variables of the device to be modeled and theoretical values of the operating variables calculated using initial guesses of modeling parameters. The objective function is minimized by calculating the gradient of the objection function to obtain a next guess point with its associated parameter values. If one of the parameter values for the next guess point violates a constraint on that parameter value, the gradient of the objective function is recalculated ignoring the particular parameter. The multiple iterations associated with the "hem-stitching" operations common with prior art systems are thus avoided.

REFERENCES:
patent: 4678947 (1987-07-01), Huijsing et al.
patent: 4962321 (1990-10-01), Hansen, Jr.
patent: 5257200 (1993-10-01), Machala, III et al.
patent: 5265028 (1993-11-01), Machala,III

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