Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2001-09-18
2004-09-14
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S540000
Reexamination Certificate
active
06791538
ABSTRACT:
FIELD OF INVENTION
This invention relates to a method and system for operating a combination unified memory and graphics controller. More specifically, the invention relates to a system which only writes back a video image on a bus when the image is changed.
BACKGROUND OF INVENTION
In current display driver configurations, the processing unit or processor and graphics display controller jointly operate on a single external memory facility, e.g. DRAM, through using the associated DRAM controller in common. This method is known as a unified memory approach and represents an extremely cost-effective solution through its limited number of components and pins.
However, with advancing display sophistication, represented by a higher number of bits per pixel, a higher number of map planes underlying a composite picture and the demand for an ever greater image resolution, in combination with a high refresh rate such as 50 or 60 times per second, raises the amount of bus-traffic necessary for maintaining the displayed image. In fact, requirements may go up to 8-bit pixels, using at least two overlay planes, and full VGA support. Without additional measures, the unified memory concept would be ruined through the incurred rise in bus traffic. Depending on the architecture chosen, the peak values of the bus load may be acceptable but the average bus load is expected to be excessively high.
By itself, frame grabbing is well-known, such as recited in U.S. Pat. No. 5,798,798 for simultaneously acquiring video images and analog signals, and U.S. Pat. No. 6,023,522 for fingerprint acquisition. However, such frame grabbing occurs for every frame of a signal sent to a display.
Thus, there is a need to maintain the advantages of unified memory while still restricting the incurred bus load to an acceptable level. There is also a need for a system where frame grabbing is applied where the image source may have its contents remain steady for relatively long intervals and the changes will occur only intermittently.
SUMMARY OF THE INVENTION
These needs and others may be met by the present invention which is embodied in an interface between various electronic subsystems that are mutually coupled through a bus facility for a display-based system. These subsystems include at least a processing unit, a memory control facility, a graphics display controller, and an external memory facility. These subsystems are collectively interconnected by a bus facility to the external memory facility. The processing unit, the memory control facility, the graphics display controller, and as the case may be, various other peripherals are joined into a single integrated circuit module. Particularly, the graphics display controller interfaces to a display facility, and has a first mode supplying the display facility a video image signal having at least one overlay plane. According to one aspect a detector is provided for detecting display stabilization and an output of the graphics display controller is coupled to a frame grabber. The frame grabber is configured for executing a writeback-to-memory storage of the video image signal into a writeback image memory during a subsequent video frame, and subsequently signaling the graphics display controller to switch over to a second mode. In the second mode, the stored writeback video image signal is supplied to the display facility for display.
The video image signal in the above display system may remain unchanged during considerable time periods. The writeback-to-memory storage of the video image signal and the signaling of a change in the video image signal to be displayed allows updating the stored writeback image only when the image changes and therefore greatly reduces the bus load compared with the prior art systems. The system has all data necessary to display the image continuously available.
A further considerable reduction of the bus load is obtained in a preferred embodiment of the system according to the invention, where the frame grabber is arranged for on-the-fly compacting coding of the video image signal into an encoded writeback video image signal. The graphics display controller includes a decoding facility for decoding an encoded writeback video image signal prior to the display thereof.
Preferably, run-length encoding is being used to effect compacting or data compression of the video image signal prior to the writeback-to-memory storage.
The detector is preferably also arranged for signaling the graphics display controller to switch over from the second mode to the first mode at a change in the video image signal to be displayed.
Another preferred embodiment of the above system according to the invention which allows for a cost effective implementation has a single integrated circuit containing the processing unit, memory control facility and display controller.
A particular embodiment features separate application and memory management facilities, each having a respective processor, a set of two memory controllers, a graphics display controller, and a block of peripheral modules. While the processing oriented architecture has been doubled in this system, the memory remains singular.
The invention also relates to a method for operating a display-based system that has various subsystems including at least a processing unit, a memory control facility, and a graphics display controller interfacing to a display facility. The graphics display controller has a first mode providing a video image signal to the display facility. These subsystems are collectively interconnected by a bus facility to an external memory facility.
A method according to the invention is characterized by generating a screen stable signal when display stabilization is detected, and having the frame grabber subsequently execute a writeback-to-memory storage of the video image signal into a writeback image memory. The graphics display controller is subsequently signaled to switch over to a second mode, in which the stored writeback video image signal is supplied to the display facility for display.
In a preferred embodiment the busload is further decreased by the writeback-to-memory storage applying to a single video overlay plane.
Preferably, this method according to the invention includes making the screen stable signal inactive upon entering a graphics handler procedure, and letting it return to active upon exiting the graphics handler procedure. This measure allows for a simple software implementation.
For reliable signaling of the graphics display controller to switch over to the stored writeback image for display, the screen stable signal is determined by calculating a video check sum at an output of the graphics display controller.
Furthermore, the screen stable signal is preferably determined through monitoring CPU accesses to memory regions that contain video data currently displayed.
In another preferred method, the writeback-to-memory storage is executed during a succession of a plurality of frame intervals, for constituting a single image.
The graphics display controller switches between the first and second modes during a vertical video signal blanking interval to avoid switching actions from becoming noticeable (e.g. in a flickering of the displayed image). Further features of the invention are recited in the dependent claims.
It is to be understood that both the foregoing general description and the following detailed description are not limiting but are intended to provide further explanation of the invention claimed. The accompanying drawings, which are incorporated in and constitute part of this specification, are included to illustrate and provide a further understanding of the method and system of the invention. Together with the description, the drawings serve to explain the principles of the invention.
REFERENCES:
patent: 5512921 (1996-04-01), Mital et al.
patent: 5854637 (1998-12-01), Sturges
patent: 5961617 (1999-10-01), Tsang
patent: 6122715 (2000-09-01), Palanca et al.
patent: 6434450 (2002-08-01), Griffin et al.
patent: 0 645 691 (1994-09-01), None
patent: 0 720
Mayer Brown Rowe & Maw LLP
Patel Nitin
Shankar Vijay
Siemens AG
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