Method and system for multilevel serializer/deserializer

Coded data generation or conversion – Digital code to digital code converters – Serial to parallel

Reexamination Certificate

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C341S101000

Reexamination Certificate

active

07342520

ABSTRACT:
A serial bit transparent data transferring technique eliminating the bit ambiguity problem of the standard time-division multiplexing/demultiplexing architecture without introduction of any extra latency. A serializer multiplexer converts input parallel data words into a serial data bit stream under control of a serializer timing circuit. An output multilevel buffer retimes the serialized data and increases the amplitude of certain bits with a preselected value to mark positions of out-going serial data words. The bits are defined by a serializer digital data converter also controlled by the same timing circuit. The imposed marking pulses are retrieved from the input serial data stream by a multilevel input detector of a deserializer timing circuit and used for the synchronization of the demultiplexing operation. As a result, the deserializer directly reconstructs the original bit order from the serial data bit stream with no extra bits, thus providing minimal possible latency and full data rate.

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patent: 6624766 (2003-09-01), Possley et al.
patent: 2003/0103509 (2003-06-01), Kendall et al.
patent: 2003/0103533 (2003-06-01), Hilgers et al.
patent: 2004/0047371 (2004-03-01), Lentine et al.

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