Method and system for multi-PHY addressing

Details Method and system for multi-PHY addressing Method and system for multi-PHY addressing

2005-06-03

2008-10-07

Chan, Wing F. (Department: 2619)

Multiplex communications

Data flow congestion prevention or control

Control of data admission to the network

C370S235000, C370S469000

Reexamination Certificate

active

07433308

ABSTRACT:
Multi-PHY addressing from source to destination in which n-number of channels or ports are used in a PHY layer device for communication with a link layer device. A single link layer to a single-PHY layer topology and a single link layer to a multi-PHY layer topology comprising multiple ports or channels receives a plurality of channels groups. Status indication signal is provided on continuous basis for the direct status for up to a predetermined number of channels.

REFERENCES:
patent: 5748018 (1998-05-01), Ishikawa
patent: 5854840 (1998-12-01), Cannella, Jr.
patent: 6195597 (2001-02-01), Yamada
patent: 6356557 (2002-03-01), Nichols et al.
patent: 6690670 (2004-02-01), Castellano
patent: 6865188 (2005-03-01), Stirling et al.
Jay Sethuram, Richard J. Weber, Chandra S. Joshi; “Method And System For Source Synchronous Clocking;” filed Nov. 29, 1999; U.S. Appl. No. 09/450,802; including Specification: pp. 1-16; Drawings: Figures 1-5 on 5 sheets.

Affiliated with

Also associated with

Rating

Method and system for multi-PHY addressing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for multi-PHY addressing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for multi-PHY addressing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4018657