Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
2003-02-13
2009-06-23
Shah, Kamini S (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C703S014000, C703S019000, C703S021000, C703S022000, C716S030000, C716S030000, C714S741000, C714S742000
Reexamination Certificate
active
07552040
ABSTRACT:
A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.
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Dorfman Barry Lee
Rosser Thomas Edward
Soreff Jeffrey Paul
Baca Matthew W.
Gebresilassie Kibrom K
Harris Andrew M.
Harris, Atty at Law, LLC Mitch
International Business Machines - Corporation
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