Method and system for minimizing the delay in executing branch-o

Details Method and system for minimizing the delay in executing branch-o Method and system for minimizing the delay in executing branch-o

1995-06-02

1998-09-01

Teska, Kevin J.

395394, 395580, 395584, G06F 938

Patent

active

058023461

ABSTRACT:
A system and method for minimizing the delay associated with executing a register dependent instruction in which the execution of the register dependent instruction is dependent on an operand of a preceding instruction. In a branch unit for executing register dependent instructions, functional units are connected via a rename bus, and the functional units are connected to a general purpose register (GPR) via a GPR bus. The system and method routes the rename bus and the GPR bus directly to an instruction fetch address register thereby enabling the branch unit to execute a register dependent instruction during the same cycle as the preceding instruction.

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