Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2010-07-13
2011-12-20
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S100000
Reexamination Certificate
active
08082529
ABSTRACT:
A method and system is described for mapping a system-level description of an integrated system directly to a technology-specific set of logic cells that are comprised primarily of large complex cells (bricks). The invention is based on applying aggressive Boolean operations that would be of impractical runtime complexity for a large library, but are applicable for the targeted brick libraries which typically contain a small number of complex cells, along with a much smaller number of simple cells. This invention is modular such that it can be applied in the context of incremental netlist optimization as well as optimization during physical synthesis.
REFERENCES:
patent: 6295636 (2001-09-01), Dupenloup
patent: 6470486 (2002-10-01), Knapp
patent: 6519609 (2003-02-01), Touzet
patent: 6836877 (2004-12-01), Dupenloup
patent: 6958545 (2005-10-01), Kotecha et al.
patent: 2003/0145288 (2003-07-01), Wang et al.
patent: 2003/0233628 (2003-12-01), Rana et al.
patent: 2006/0075375 (2006-04-01), Rana et al.
patent: 2007/0011643 (2007-01-01), Wang et al.
patent: 2008/0127000 (2008-05-01), Majumder et al.
Keutzer, K., “Dagon: Technology Binding and Local Optimization”, 24thACM/IEEE Design Automation Conf., pp. 341-347 (1987).
Kukimoto, Y., et al., “Delay-Optimal Technology Mapping by DAG Covering”,Whitepaper, pp. 348-351 (1998).
Lehman, et al., “Logic Decomposition During Technology Mapping”, IEEE Trans. CAID, 16(8), 1997, pp. 813-833.
Motiani, D., “Implementation Flow for Design Using Regular Fabric Logic Bricks”, Carnegie Mellon Univ. Whitepaper, Aug. 2005, pp. 1-31.
Sentovich, E.M., et al., “SIS: A system for Sequential Circuit Synthesis”, Dept. of Elec. Engineering and computer Sci, Univ. CA Berkeley whitepaper, May 4, 1992, pp. 8-16.
Dimyan Magid
Do Thuan
PDF Solutions, Inc.
Pillsbury Winthrop Shaw & Pittman LLP
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