Method and system for manufacturing a semiconductor device...

Details Method and system for manufacturing a semiconductor device... Method and system for manufacturing a semiconductor device...

2008-10-24

2011-10-18

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S055000, C716S126000, C716S139000

Reexamination Certificate

active

08042081

ABSTRACT:
A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured to store parameters indicating the parasitic resistance and the parasitic capacitance in relation to the target interconnection to each of the plurality of patterns. The producing is achieved by calculating the parameters to a plurality of conditions corresponding to deviation in manufacture of the wiring structure for each of the plurality of patterns.

REFERENCES:
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Tomohiro Fujita et al., Statistical Delay Calculation With Vector Synthesis Model, Transactions of information Processing Society of Japan, Information Processing Society of Japan, Apr. 2000, pp. 927-934, vol. 41, No. 4.
Kenta Yamada, USPTO Office Action, U.S. Appl. No. 12/213,412, Feb. 18, 2011, 8 pages.
Kenta Yamada, USPTO Office Action, U.S. Appl. No. 12/213,412, Jun. 29, 2011, 8 pages.

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