Data processing: database and file management or data structures – Database design – Data structure types
Reexamination Certificate
1995-07-26
2002-03-12
Black, Thomas (Department: 2171)
Data processing: database and file management or data structures
Database design
Data structure types
C707S793000, C712S034000, C712S218000, C712S219000, C712S228000, C712S230000, C712S233000, C712S234000, C712S236000
Reexamination Certificate
active
06356918
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to an improved data processing system, and in particular to a method and system for managing addressable registers in a data processing system. More particularly, the present invention relates to a method and system for controlling and monitoring a register array in a data processing system that processes out of sequence instructions, and a method and system that provides register content restoration upon the occurrence of an interrupt condition or the determination that instructions in a mispredicted branch have been executed.
2. Description of the Related Art:
The design of a typical computer data processing system requires the establishment of a fixed number of addressable registers, such as general purpose registers (GPR's) and floating-point registers (FPR's), for the programmer to use in designing programs for the data processing system. Changing the number of architecturally available registers once a system is available would require substantial rewriting of programs to make use of the newly added registers.
The design of computers and computer programs is also based on the assumption that computer data processing system program instructions are executed by the data processing system in the order in which they are written in the program and loaded into the data processing system. While instructions must logically appear to the data processing system to have been executed in program order, it has been learned in an effort to improve computer performance that some instructions do not have to be physically performed in program order, provided that certain dependencies do not exist with other instructions. Further, if some instructions are executed out-of-order, and one of such instructions is a branch instruction, wherein a branch prediction is made to select the subsequent instruction sequence, a need to restore the registers affected by instructions in the predicted branch to their original values can occur if the branch is mispredicted. In such a case, the data processing system is restored to the condition before the branch was taken. The process of efficiently executing instructions out of order requires that values for registers prior to the predicted branch be maintained for registers affected by the instructions following the branch, while provision is made to contingently store new values for registers affected by instructions following the predicted branch. When branch instructions are resolved, the contingency of the new register values is removed, and the new values become the established values for the registers.
Large processors have for many years employed overlapping techniques under which multiple instructions in the data processing system are in various states of execution at the same time. Such techniques may be referred to as pipelining. Whenever pipelining is employed, control logic is required to detect dependencies between instructions and alter the usual overlapped operation so that results of the instructions are those that follow the one-instruction-at-a-time architectural data processor model. In a pipelined machine, separate hardware is provided for different stages of an instruction's processing. When an instruction finishes it's processing at one stage, it moves to the next stage, and the following instruction may move into the stage just vacated.
In many pipelined machines, the instructions are kept in sequence with regard to any particular stage of its processing, even though different stages of processing for different instructions are occurring at the same time. If the controls detect that a result that has not yet been generated is needed by some other executing instruction, the controls must stop part of the pipeline until the result is generated and passed to the part of the pipeline where it is needed. Although this control logic can be complex, keeping instructions in sequence in the pipeline helps to keep the complexity under control.
A more complex form of pipelining occurs if the data processing system includes separate execution units. Because different instructions have different execution times in their particular type of execution unit, and because the dependencies between instructions will vary in time, it is almost inevitable that instructions will execute and produce their results in a sequence different from the program order. Keeping such a data processing system operating in a logically correct manner requires more complex control mechanisms than that required for pipeline organization.
One problem that arises in data processing systems having multiple executions units is providing precise interrupts at arbitrary points in program execution. For example, if an instruction creates an overflow condition, by the time such overflow is detected, it is entirely possible that a subsequent instruction has already executed and placed a result in a register or in main storage—a condition that should exist only after the interrupting instruction has properly executed. Thus, it is difficult to detect an interruption and preserve status of the data processing system with all prior but no subsequent instructions having been executed. In this example, the overflow interrupt will actually be recognized later than it occurred. Other similar situations are possible in the prior art.
Designers of some prior art data processing systems chose to handle interrupts by allowing all instructions that were in some state of execution at the time of the interrupt to complete their execution as much as possible, and then take an “imprecise” interruption which reported that some instruction in the recent sequence of instructions had created an interrupt condition. This may be a reasonable way to handle interrupts for conditions such as overflow, where results will be returned to a programmer who will fix a program bug or correct the input data, and then rerun the program from the beginning. However, this is an unacceptable way to handle interrupts like page faults, where the system program will take some corrective action and then resume execution from the point of interruption.
Applicant is aware of U.S. Pat. No. 4,574,349, in which additional registers are provided to be associated with each GPR and in which register renaming occurs with the use of a pointer value. However, this patent does not solve the problem of precise recovery from interrupts or recovery from incorrectly guessed branches during out-of-order execution.
In an article in the IBM Technical Disclosure Bulletin, entitled “General Purpose Register Extension,” August, 1981, pages 1404-1405 discloses a system for switching between multiple GPR sets to avoid use of storage when switching subroutines. Another article in the IBM Technical Disclosure Bulletin, entitled “Vector-Register Rename Mechanism,” June, 1982, pages 86-87 discloses the use of a dummy register during instruction execution. When execution is complete, the register is renamed as the architected register named by the instruction for receiving results. During execution, the register is transparent and this allows for extra physical registers. However, neither of these articles deals with the problems caused by out-of-order instruction execution.
An article in the IBM Technical Disclosure Bulletin, entitled “Use of a Second Set of General Purpose Registers to Allow Changing General-Purpose Registers During Conditional Branch Resolutions,” August, 1986, pages 991-993 shows a one-for-one matched secondary set of GPRs to hold the original GPR contents during conditional branch resolution so that such GPR contents may be used to restore the system status if necessary. Conditional mode tags are used with the GPRs to regulate status of the registers, or to restore the original contents of the register.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved data processing system.
It is another object of the present invention to provide a method and system for managing addressab
Chuang Chiao-Mei
Le Hung Qui
Black Thomas
Bracewell & Patterson L.L.P.
England Anthony V.S.
Mizrahi Diane D.
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