Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2001-04-19
2002-11-05
Young, Brian (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S155000
Reexamination Certificate
active
06476741
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to production testing of integrated electronic circuits, and particularly to testing of analog-to-digital converter (“ADC”) circuits as they are produced to determine their functional specifications.
ADCs are characterized by functional specifications., such as integral nonlinearity (“INL”) and differential nonlinearity (“DNL”). To determine whether a given ADC that has been manufactured meets the required specifications, it must be tested. Conventional testing of ADCs as they are produced involves direct measurement of their functional specifications. However, as ADCs continue to improve in resolution, direct measurement has become more time time consuming and expensive. The measurement of INL and DNL, that is, linearity testing, constitutes the major portion of the ADC test time (35-50%) and, therefore, the major portion of the test cost for ADCs.
The measurement of INL and DNL involves the measurement of all the code transitions voltages (“CTs”) (the voltage input at which the output code of an ADC changes) of an ADC. In response to the problem of increasing test times, various techniques have been developed that estimate all of the CTs from a subset of CT measurements. Such techniques are described, for example, in: 117 G. N. Stenbakken and T. M. Souders, “Test-Point Selection and Testability Measures via QR Factorization of Linear Models,”
IEEE Transactions on Instrumentation and Measurement
, Vol. IM-36, No. 2. June 1987, pp 406-410 (“Stenbakken and Souders I”); T. M. Souders and G. N Stenbakken. “A Comprehensive Approach to Modeling and Testing of Mixed-signal Devices,”
Proceding of IEEE International Test Conference
, 1990, pp 169-176 (“Souders and Stenbakken”); G. N. Stenbakken and T. M. Souders. “Linear Error Modeling of Analog and Mixed-Signal Devices,”
Proceeding of IEEE Internationial Test Conference
, 1991, pp 573-581 (“Stenbakken and Souders II”); G. N. Stenbakken and T. M. Souders, “Developing Linear Error Models for Analog Devices,”
IEEE Transactions on Instrumentation and Measurements
, Vol. 43, No. 2, April 1994, pp 157-163 (“Stenbakken and Souders III”); and T. D. Lyons, The Production Implementation of a Linear Error Modeling “Technique,”
Proceeding of IEEE International Test Conference
, 1992, pp 399-404 (“Lyons”).
Techniques such as those described in the aforementioned references are based on two assumptions. First, for most high resolution ADCs, the number of variables, such as the values of resistors, capacitors and transistor transconductances, which control their linearity is much less than the total number of CTs. Second, the variations in these variables is typically small so that the relationship between these variables and the corresponding CTs can be well approximated by a linear function. second order or higher order terms being negligible. Techniques for using a linear model with three different production test methods to save test time have been described in P. D. Capofreddi and B. A. Wooley, “The Use of Linear Models in A/D Converter Testing,”
IEEE transactions on Circuits and Systems
-
I: Fundamental Theory and Applications
, Vol. 44, No. 12, December 1997, pp 1105-1113 (“Capofreddi and Wooley I”), and P. D. Capofreddi and B. A. Wooley, “The Use of Linear Models for the Efficient and Accurate Testing of A/D Converters,”
Proceeding of IEEE International Test Conference
, 1995, pp 54-60 (Capofreddi and Wooley II”).
INL and DNL are measures of how much the CTs of an ADC differ from ideal linear behavior. Specifically, DNL is a measure of the deviation from the ideal 1 least significant bit (“LSB”) of the voltage span that is associated with each output code. INL is the worst case deviation of an ADC transfer function from the line between the measured end points (zero and full scale) of the ADC. INL and DNL are usually expressed in LSBs. These measures are illustrated on FIG.
1
.
DNL and INL can be expressed in terms of the CTs as:
DNL
i
=
(
γ
i
-
γ
i
·
1
1
LSB
)
-
1
(
1
)
INL
i
=
γ
i
-
γ
1
-
(
(
γ
2
′′
-
1
-
γ
1
)
/
(
2
′′
-
2
)
)
·
(
i
-
1
)
1
LSB
(
2
)
where &ggr;
i
is the i
th
CT,
n is the number of bits in the ADC, and
1LSB denotes the ideal voltage span of 1 LSB of the ADC.
Since INL and DNL can be easily computed with a few algebraic operations once the CTs are known, the task in determining the INL and DNL is to determine the CTs, that is, the &ggr;
i
s. INL and DNL measurements usually involve the measurement of all the CTs of an ADC. At least three different techniques can be used for the measurement of INL and DNL of ADCs, as described in S. Max, “Fast Accurate and Complete ADC Testing,”
Proceeding of IEEE International Test Conference
, 1989, pp 111-117 (hereinafter “S. Max”). The three techniques are (i) the servo-loop method, (ii) the ramp histogram method (tally and weight method) and (iii) the sine wave histogram method (aka code density method). The servo loop method involves the use of an analog integrator in a feedback loop and has a long test time because of the large settling time of the integrator and the long conversion time of the DC voltmeter used to measure code transitions. A fast variant of the servo-loop method using an accurate digital-to-analog converter in a feedback loop is described in S. Max, supra, but this requires a more complex interface board design for the Device-Under-Test (“DUT”) and a non-standard test interface. Therefore, linearity testing of most ADCs is performed using the ramp histogram technique. T. Kuyel, “Linearity Testing Issues of Analog to Digital Converters,”
Proceeding of IEEE International Test Conference
, 1999, pp 747-756. The sine wave histogram technique has a worst-case error in linearity measurements that is &pgr; times the error of a ramp of the same test length (test time) and therefore is used only in cases where generation of a ramp with the required linearity is not possible. J. Doemberg, Hae-Seung Lee and D. A. liodges, “Full-Speed Testing of A/D Converters,”
IEEE Journal of Solid-State Circuits
, Vol. SC-19, NO. 6, December 1984, pp 820-827. The servo-loop method measures CTs one at a time, while the histogram techniques estimate all the CTs in one pass. Therefore, the histogram methods are inherently faster. In the ramp histogram method for estimating CTs, a linear ramp or triangular wave is applied to the input of the ADC and a histogram of the output codes is computed. The CTs are estimated from the histogram using
γ
i
=
V
0
+
(
V
F
-
V
0
)
N
·
(
∑
j
=
0
i
c
i
)
where V
0
is the initial (minimum) value of the ramp,
V
F
is the final (maximum) value of the ramp,
c
i
is the number of occurrences of code i, and
N is the total number of samples in the histogram.
The INL and DNL can also be directly computed from the histogram without the computation of the CTs. For computing the DNL using a triangular wave or linear ramp, the probability that the input voltage is within a given interval is directly proportional to the width of the interval. Consequently, the width of each code (the voltage interval of the input voltage for which the output is equal to a given code) will be proportional to the number of occurrences of the given code in the histogram. Therefore, an estimate of the DNL of the ADC is given by
DNL
i
=
c
i
(
∑
j
=
1
2
′′
2
c
j
)
/
(
2
′′
-
2
)
-
1
The input waveform span is usually set to be slightly larger than the input range of the ADC to ensure occurrence of all codes. Therefore the first and last code counts are ignored in the DNL computation. The INL, for the ADC is given by
INL
i
=
∑
j
=
1
i
DNL
[
j
]
These equations give the same DNL and INL, respectively, as those computed by Equations 1 and 2, above.
The number of variables that control the CTs of an ADC is much less than the number of CTs. The CTs have, therefore, been modeled by a linear model. Stenbakken and Souders I;
Chatterjee Abhijit
Cherubal Sasikumar
Birdwell Janke & Durando, PLC
Georgia Tech Research Corp.
Nguyen John
Young Brian
LandOfFree
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