Method and system for maintaining hierarchy throughout the integ

Details Method and system for maintaining hierarchy throughout the integ Method and system for maintaining hierarchy throughout the integ

1997-04-28

2000-03-07

Teska, Kevin J.

39550012, G06F 1750

Patent

active

060351063

ABSTRACT:
A method and system for translating abstract structural or behavioral circuit descriptions to physically implementable files, preferably suitable for use in a Field Programmable Gate Array (FPGA) or other programmable device. A selection of layouts are generated for a cell definition (a function), allowing optimization and acceleration of circuit placement and routing without compromising design hierarchy or altering design function. Layout transformation functions may be manually initiated or automatically selected and applied during implementation of a placement algorithm.

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Kirkpatrick, S.; Gelatt, C. D., Jr.; Vecchi, M. P., "Optimization by Simulated Annealing," Science, vol. 220, pp. 671-680, May 13, 1983.
Xilinx, Inc., "XC6200 FPGA Family", Advanced Produced Description, 1996, pp. 3-2 to 3-52.

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