Method and system for low cost line buffer system design

Details Method and system for low cost line buffer system design Method and system for low cost line buffer system design

2004-12-20

2008-11-18

Peikari, B. James (Department: 2189)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C710S053000, C710S052000, C365S230040, C365S189050, C711S168000, C711S219000

Reexamination Certificate

active

07453761

ABSTRACT:
Various aspects of the low cost line buffer system allow a reduction in circuitry versus conventional approaches to line buffer design. A plurality of line buffers such that the output of one line buffer in the plurality of line buffers may be coupled to an input of a succeeding line buffer in the plurality of line buffers. A first line buffer in the plurality of line buffers may be coupled to an input write data signal, while the width of a subsequent plurality of line buffers may be less than or equal to the width of the previous line buffers in the plurality of line buffers.

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