Method and system for logic verification using mirror interface

Details Method and system for logic verification using mirror interface Method and system for logic verification using mirror interface

2005-03-08

2005-03-08

Nghiem, Michael (Department: 2863)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

Reexamination Certificate

active

06865502

ABSTRACT:
Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

REFERENCES:
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patent: 5146474 (1992-09-01), Nagler et al.
patent: 5414695 (1995-05-01), Nagler et al.
patent: 5668745 (1997-09-01), Day
patent: 6539522 (2003-03-01), Devins et al.

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