Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2006-11-07
2006-11-07
Vital, Pierre (Department: 2188)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
07133999
ABSTRACT:
A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”) devices. Each group of eight PEs can access respective groups of eight columns in a respective SRAM device. Each PE includes a local column address register that can be loaded through a data bus of the respective PE. A local column address stored in the local column address register is applied to an AND gate, which selects either the local column address or a column address applied to the AND gate by the central control unit. As a result, the central control unit can globally access the SRAM device, or a specific one of the eight columns that can be accessed by each PE can be selected locally by the PE.
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Dorsey & Whitney LLP
Micron Technology,Inc.
Vital Pierre
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