Patent
1997-09-30
1999-12-28
Teska, Kevin J.
G06F 1750
Patent
active
060092513
ABSTRACT:
A method and system for performing layout verification on an integrated circuit (IC) design using reusable subdesigns. Many custom designed integrated circuits are designed and fabricated using a number of computer implemented automatic design processes. Within these processes, a high level design language (e.g., HDL or VHDL) description of the integrated circuit can be translated by a computer system into a netlist of technology specific gates and interconnections there between. The cells of the netlist are then placed spatially in an integrated circuit layout and the connections between the cells are routed using computerized place and route processes. Circuit designers next run layout verification tests on the layout to verify that the geometry and connectivity data of the design meets specific design rules and matches logically with the schematic representation. The present invention provides a method of layout verification where unchanged subdesigns of a hierarchical IC design can be reused upon subsequent verification processes of the same IC design. They are reused for both design rule checking (DRC) and layout versus schematic (LVS) comparison. By reusing some of the subcell designs, subsequent verification processes of the present invention can be performed very efficiently. To account for faults attributed to subcell interfaces, the present invention advantageously determines subcell overlap areas within the layout and selectively flattens and verifies these areas in addition to any subcell designs that were not previously validated. Further, the invention determines updated connectivity information for new subcell designs.
REFERENCES:
patent: 5050091 (1991-09-01), Rubin
patent: 5281558 (1994-01-01), Bamji et al.
patent: 5528508 (1996-06-01), Russell et al.
patent: 5544067 (1996-08-01), Rostoker et al.
patent: 5604680 (1997-02-01), Bamji et al.
patent: 5625564 (1997-04-01), Rogoyski
patent: 5629861 (1997-05-01), Kim
patent: 5787006 (1998-07-01), Chevallier et al.
Martin E. Newell, Daniel T. Fitzpatrick; "Exploiting Structure in Integrated Circuit Design Analysis"; Jan. 26, 1982; Xerox Palo Alto Research Centers and Computer Science Division University of California, Berkeley, 1982 Conference on Advanced Research in VLSI, M.I.T. pp. 84-92.
Nunes et al. ("A new approach to perform circuit verification using O(n) algorithms", IEEE, Proceedings of the 20th EUROMICRO Conference: System Architecture and Integrations, Sep 5, 1994, pp. 428-432).
Hedenstierna et al. ("The halo algorithm--an algorithm for hierarchical design of rule checking of VLSI circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 2, Feb. 1993, pp. 265-272).
Stevens et al.("An Integrated Approach for Hierarchical Verification of VLSI Mask Artwork", IEEE Journal of Solid-State Circuits, vol. Sc-20, No. 2, Apr. 1985, pp. 501-509).
Hedenstierna et al. ("The use of inverse layout trees for hierarchical design verification", IEEE International Conference on Computer-Aided Design, ICCAD-88, Nov. 7, 1988, pp. 534-537).
Goering ("Avant! Launches Hercules verification Tool", Electronic Engineering Times, No. 924, p. 100 (1-2), Oct. 21, 1996).
Ho Wai-Yan
Tang Hongbo
Kik Phallaka
Synopsys Inc.
Teska Kevin J.
LandOfFree
Method and system for layout verification of an integrated circu does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and system for layout verification of an integrated circu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for layout verification of an integrated circu will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2388461