Method and system for interrupt handling in a multi-processor co

Details Method and system for interrupt handling in a multi-processor co Method and system for interrupt handling in a multi-processor co

1997-08-18

2000-02-29

Follansbee, John A.

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

712 26, 712 30, 710260, 710261, G06F 930

Patent

active

060322454

ABSTRACT:
In the system bus controller of a multi-processor system, apparatus is provided for selecting one of the processors to handle an interrupt. A mask is provided for each respective task being executed on each one of the processors. Each mask includes a speculation bit identifying whether the task is speculative. Each mask includes a plurality of class enable bits identifying whether the task can be interrupted by a respective class of interrupts associated with each of the plurality of class enable bits. Control lines in the system bus receive an interrupt having a received interrupt class. A subset of the processors is identified; processors in the subset can be interrupted by the received interrupt based on the received interrupt class and the respective speculation bit and class enable bits assigned to the task being executed on each respective processor. A Boolean AND operation is performed on the mask associated with the respective task executing on each processor. The AND operation is performed on the speculation bit and the class enable bit which corresponds to the received interrupt class, so as to determine whether that processor is included in the subset. One of the processors in the subset is selected to process the received interrupt, if the subset includes at least one processor.

REFERENCES:
patent: 5179702 (1993-01-01), Spix et al.
patent: 5283904 (1994-02-01), Carson et al.
patent: 5627992 (1997-05-01), Baror
patent: 5701496 (1997-12-01), Nizar et al.
patent: 5812811 (1998-09-01), Dubey et al.

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