Method and system for interpolating baud rate timing recovery fo

Pulse or digital communications – Repeaters – Testing

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375 95, 375117, 307354, H04L 2538, H04L 2706

Patent

active

052630544

ABSTRACT:
An apparatus for efficient computation of a demodulation process on a digital signal processor for a sampled signal, which includes programming a digital signal processor to apply the sampled signal to an interpolating filter to add interpolation samples to the sampled signal, to search the sampled signal for a threshold crossing associated with a start bit, performing a linear interpolation to find a point where the threshold crossing occurs when a threshold crossing is detected, responsive to determining the point of the threshold crossing, determining a center of a start bit when the point of the threshold crossing has been determined, calculating a supplemental delay, and determining center points for subsequent of data bits utilizing the supplemental delay period from the center of the start bit.

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patent: 4378526 (1983-03-01), Champagne et al.
patent: 4412339 (1983-10-01), Alfke et al.
patent: 4794341 (1988-12-01), Barton et al.
patent: 5040192 (1991-08-01), Tjahjadi

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