Patent
1997-09-18
1999-07-27
Ray, Gopal C.
395841, G06F 1314, G06F 1300
Patent
active
059304847
ABSTRACT:
A method and system for input/output control in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously in response to one or more transfer requests. In response to a transfer request having a data address associated therewith, a particular target device is identified. The data address is then written into an address queue. Thereafter, one or more of the multiple sub-buses are utilized to transfer data to or from a single processor in response to a transfer request from a single processor. In response to a transfer request from multiple processors, one or more of the multiple sub-buses may be utilized separately to simultaneously transfer data to or from multiple processors.
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Kahle James Allan
Tran Cang Ngoc
Dillon Andrew J.
England Anthony V. S.
International Business Machines - Corporation
Ray Gopal C.
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