Method and system for initial state determination for instructio

Details Method and system for initial state determination for instructio Method and system for initial state determination for instructio

1996-11-25

1999-04-13

Peeso, Thomas

395444, 395445, H04B 1700

Patent

active

058945750

ABSTRACT:
A method and system for determining an initial architectural state for instruction trace reconstruction. Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyses and timing. One well-known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine instruction addresses, data addresses and data during the trace. However, the initial architectural state (the state of all caches, buffers and registers) must be determined in order to accurately reconstruct an instruction trace. At least one cache within the processor system is divided into two portions, the content of that cache is invalidated and each cache entry thereafter is duplicated within each portion of the divided cache. Upon initiation of an instruction trace, one half of the cache is frozen, preserving the initial state of the system with respect to that cache without requiring the cache to be invalidated and refilled during the instruction trace, so that the initial state may be utilized to reconstruct an instruction trace in combination with the monitored bus traffic.

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H. Dwyer Et Al., "Technique For Speculatively Sampling Performance Parameters" IBM Technical Disclosure Bulletin, vol. 37, No. 09, pp. 589-592, Sep. 1994.

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