Method and system for increased system memory concurrency in a m

Details Method and system for increased system memory concurrency in a m Method and system for increased system memory concurrency in a m

1996-08-20

1998-05-26

Kim, Matthew M.

395415, 395471, G06F 1210, G06F 1516

Patent

active

057581207

ABSTRACT:
A method and system for increasing memory concurrency in a multiprocessor computer system which includes system memory, multiple processors coupled together via a bus, each of the processors including multiple processor units for executing multiple instructions and for performing read, write and store operations and an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses within the system memory. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields, an effective address and an associated real memory address for a selected system memory location. A reference bit is provided within a first individually accessible field in each page table entry and this reference bit is utilized to indicate if an associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and this change bit is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate accessible fields the reference bit and change bit may be concurrently updated by multiple processors, increasing memory concurrency.

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