Method and system for increased instruction dispatch efficiency

Details Method and system for increased instruction dispatch efficiency Method and system for increased instruction dispatch efficiency

1994-08-12

1999-11-02

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

712200, 712208, 712214, G06F 938

Patent

active

059788968

ABSTRACT:
A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.

REFERENCES:
patent: 4081612 (1978-03-01), Hafner
patent: 4261035 (1981-04-01), Raymond
patent: 4754457 (1988-06-01), Bright et al.
patent: 4819151 (1989-04-01), May
patent: 5127091 (1992-06-01), Boufarah et al.
patent: 5202975 (1993-04-01), Rasbold et al.
patent: 5283899 (1994-02-01), Cook et al.
"Control System for Instruction Processing Order", Patent Abstracts of Japan, vol. 6, No. 96, Jun. 4, 1982.

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