Method and system for improving memory interface data integrity

Details Method and system for improving memory interface data integrity Method and system for improving memory interface data integrity

2008-04-01

2008-04-01

Mai, Lam T. (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Adaptive coding

C341S050000

Reexamination Certificate

active

07352299

ABSTRACT:
An integrated circuit (IC) for optimizing data presentation to an external memory interface bus is provided. The IC is in communication with the external memory via the external memory interface bus. The IC includes an encoder that may encode the data that are being sent to an external memory. The encoder encodes the data based on the logic value of the majority of bits in the data. The encoder sets a status bit to indicate that the data are encoded. The encoder includes two encoding stages to further enhance the data integrity and transfer. Further connected in series with the encoder is a parity generator that sets the parity bit logic value based on whether the number of logic 1s in the data, including the status bit, is even or odd. The IC also includes a parity checker to detect whether any error occurred in the data during transmission. The decoder within the IC decodes the data to the original data. The decoder is connected in series with the parity checker.

REFERENCES:
patent: 5526199 (1996-06-01), Seki et al.
patent: 6654562 (2003-11-01), Murata
patent: 6950448 (2005-09-01), Tornetta et al.
patent: 7102544 (2006-09-01), Liu
patent: 7113703 (2006-09-01), Murata

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