Method and system for implementing relative time discriminations

Details Method and system for implementing relative time discriminations Method and system for implementing relative time discriminations

1995-07-05

1998-02-24

Pan, Daniel H.

Boots, shoes, and leggings

36471504, 3647151, 395557, G06F 106, G06F 702, G06F 9305

Patent

active

057219443

ABSTRACT:
A data transmission network congestion control mechanism requires knowledge of the sequence of occurrence of two dates d1 and d2, respectively defined by times t1 and t2 provided by a wraparound timer as respective numbers A and B coded in a 2's-complement form. Relative date discrimination is implemented by dividing the wraparound timer period into four consecutive intervals, each defined by the two most significant bits of the timer count. The value of the most significant bits and the sign of A-B, are used to derive a one-bit "X" indicator, the binary value of which indicates which of the two dates d1 and d2 was first to occur.

REFERENCES:
patent: 3971005 (1976-07-01), Bulrer
patent: 4623846 (1986-11-01), LaMarchia
patent: 4905178 (1990-02-01), Mor et al.
patent: 5157655 (1992-10-01), Hamlin, Jr. et al.
IEEE Journal of Solid-Stae Circuits, vol. 27, No. 11, Nov. 1992, New York US pp. 1634-1643 H.J. Chao et al. `A VLSI Sequencer Chip for ATM Traffic Shaper and Queue Manager`.

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