Method and system for implementing partial reconfiguration...

Details Method and system for implementing partial reconfiguration... Method and system for implementing partial reconfiguration...

2011-06-28

2011-06-28

Rossoshek, Helen (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S110000, C716S111000, C716S129000, C716S130000, C716S131000, C716S136000, C716S139000, C703S014000

Reexamination Certificate

active

07971173

ABSTRACT:
Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design.

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