Method and system for implementing parity error recovery schemes

Details Method and system for implementing parity error recovery schemes Method and system for implementing parity error recovery schemes

1996-11-15

1998-07-21

Chung, Phung M.

Excavating

371 48, G06F 1110, H03M 1300

Patent

active

057843945

ABSTRACT:
A method and apparatus in a data processing system having a plurality of node controllers and a memory unit for each of the node controllers. Each one of the node controllers including at least one processor having a cache. Each memory unit including a plurality of entries each having an exclusive bit, an address tag, and an inclusion field. Each bit of the inclusion field representing one of the node controllers. The method and apparatus allow error recovery for errors occurring within the entries without using the ECC implementation. Specifically, two parity bits are used for detecting errors within an entry and logic for flushing any cache lines represented by the entry in error. The method and apparatus also includes means for detecting persistent errors and for indicating whether the error is generated by either hardware or software.

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